Abstract: Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.

Abstract: Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.