Abstract: Apparatus and method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received; and combining the results of the calculating step and the generating step.

Abstract: A method for translating data packets from one network protocol to another is disclosed. A set of translation templates is constructed. The translation templates are then loaded into a translation template cache. In response to a data packet from a first network arriving at a translation router, an appropriate translation template is selected from the set of translation templates within the translation template cache according to the translation context of the data packet. Next, a new header for transmission into a second network is constructed by reading header fields of the data packet from the first network along with the appropriate translation template in the translation template cache. The data payload of the data packet from the first network is subsequently removed from the header of the data packet and then appended to the constructed header of the second network. Finally, the newly constructed data packet is transmitted to the second network.

Abstract: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Abstract: The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area.

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames.

Abstract: Method of generating cyclic redundancy checks (CRCS) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.

Abstract: A subscriber to a service that monitors user behavior first registers with that service and selects a model of user behavior. The service then transmits that model to an agent, situated capable of monitoring user behavior and relating it to the model. After the monitoring interval the agent transmits data from the model to a server, where that data is summarized and reports created. These reports can then be sent to the subscriber in satisfaction of their needs for behavioral information.

Abstract: A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.

Abstract: A method for translating data packets from one network protocol to another is disclosed. A set of translation templates is constructed. The translation templates are then loaded into a translation template cache. In response to a data packet from a first network arriving at a translation router, an appropriate translation template is selected from the set of translation templates within the translation template cache according to the translation context of the data packet. Next, a new header for transmission into a second network is constructed by reading header fields of the data packet from the first network along with the appropriate translation template in the translation template cache. The data payload of the data packet from the first network is subsequently removed from the header of the data packet and then appended to the constructed header of the second network. Finally, the newly constructed data packet is transmitted to the second network.

Abstract: A method of calculating partial CRCs on-the-fly is provided without the need for pre-computed tables and without size restrictions on data blocks or packets. The method works for both fixed and variable length data blocks by computing the remainders of the powers of two as data blocks are received, without the need for pre-computing them and storing them in a table. The method may be employed on data streams wherein the data blocks are received out-of-order.

Abstract: A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type.

Abstract: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Abstract: A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.