Abstract: A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Abstract: A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays—on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

Abstract: A system and method using thermal feedback to cooperatively vary a voltage and frequency of a circuit to control heating while maintaining synchronization. Preferably, on-chip thermal sensors are used for feedback.

Abstract: In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor.

Abstract: A system and method using thermal feedback to cooperatively vary a voltage and frequency of a circuit to control heating while maintaining synchronization. Preferably, on-chip thermal sensors are used for feedback.

Abstract: A system and method for modulating the switching factor of a circuit to control heating and which does not require modulation of the circuit's clock frequency. The switching factor refers to the fact that due to gating requirements, latency and data transfer characteristics, the rate at which a circuit's inputs are addressed is some fraction of the circuit clock frequency. Application can be made to many existing systems which incorporate single or multiple VLSI circuits such as superscalar microprocessors, parallel processors, DSPs, microcontrollers and MPEG decoders.

Abstract: A system and method for optimizing power consumption by a disk drive unit. The system and method monitor and analyze historical use data and calculate a predicted inactivity duration. The predicted inactivity duration is used to power-down the rotational speed of the drive to the first of one or more intermediate rotational speeds. Continued inactivity will result in further speed reduction until the drive is ultimately powered off. The drive increases rotational speed on demand.

Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.