Abstract: Methods and systems for calibrating a multi-mode, multi-standard transmitter and receiver are disclosed. Aspects of the method may include configuring calibration paths in a transceiver on a chip including a plurality of Tx and Rx paths. IP2 distortion may be calibrated for the Rx paths utilizing a phase locked loops in the chip and the configurable calibration paths. Local oscillator leakage, Rx path DC offset and RSSI, Tx and Rx I and Q mismatch, and Tx and Rx path filters may be calibrated utilizing the plurality of configurable calibration paths. Cutoff frequency of the filters in the Tx and Rx paths may be calibrated. Blocker signals may be mitigated by calibrating amplifier gains in the Rx paths. The calibration paths may include an envelope detector. Local oscillator leakage and I and Q mismatch may be mitigated utilizing pre-distortion generated by an on-chip digital signal processor in the Tx paths.

Abstract: Methods and systems for calibrating a multi-mode, multi-standard transmitter and receiver are disclosed. Aspects of the method may include configuring calibration paths in a transceiver on a chip including a plurality of Tx and Rx paths. IP2 distortion may be calibrated for the Rx paths utilizing a phase locked loops in the chip and the configurable calibration paths. Local oscillator leakage, Rx path DC offset and RSSI, Tx and Rx I and Q mismatch, and Tx and Rx path filters may be calibrated utilizing the plurality of configurable calibration paths. Cutoff frequency of the filters in the Tx and Rx paths may be calibrated. Blocker signals may be mitigated by calibrating amplifier gains in the Rx paths. The calibration paths may include an envelope detector. Local oscillator leakage and I and Q mismatch may be mitigated utilizing pre-distortion generated by an on-chip digital signal processor in the Tx paths.