Patents by Inventor Christy S Tyberg
Christy S Tyberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150060856Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Christy S. TYBERG, Katherine L. SAENGER, Jack O. CHU, Harold J. HOVEL, Robert L. WISNIEFF, Kerry BERNSTEIN, Stephen W. BEDELL
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Patent number: 8569803Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: August 13, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Patent number: 8445377Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: GrantFiled: September 9, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Patent number: 8441042Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: September 17, 2009Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Publication number: 20120305929Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Patent number: 8278155Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: GrantFiled: May 4, 2011Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
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Publication number: 20110318942Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: International Business Machines CorporationInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Patent number: 8017522Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: GrantFiled: January 24, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Publication number: 20110207286Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Inventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
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Patent number: 7960808Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: GrantFiled: August 23, 2007Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
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Patent number: 7879717Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: GrantFiled: June 17, 2008Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Patent number: 7755921Abstract: In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.Type: GrantFiled: August 14, 2007Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Solomon Assefa, Michael C. Gaidis, Eric A. Joseph, Stuart Stephen Papworth Parkin, Christy S. Tyberg
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Patent number: 7737561Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.Type: GrantFiled: January 3, 2008Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Kaushik A Kumar, Kelly Malone, Christy S Tyberg
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Publication number: 20100006850Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: September 17, 2009Publication date: January 14, 2010Inventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
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Publication number: 20090294925Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: ApplicationFiled: August 8, 2009Publication date: December 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Patent number: 7598169Abstract: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.Type: GrantFiled: February 21, 2007Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Elbert E. Huang, Christy S. Tyberg, Ronald A. DellaGuardia
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Publication number: 20090046493Abstract: In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.Type: ApplicationFiled: August 14, 2007Publication date: February 19, 2009Inventors: SOLOMON ASSEFA, Michael C. Gaidis, Eric A. Joseph, Stuart Stephen Papworth Parkin, Christy S. Tyberg
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Patent number: 7491965Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.Type: GrantFiled: May 28, 2008Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James P. Doyle, Bruce G. Elmegreen, Lia Krusin-Elbaum, Chung Hon Lam, Xiao Hu Liu, Dennis M. Newns, Christy S. Tyberg
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Publication number: 20080254612Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, O?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.Type: ApplicationFiled: June 17, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
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Patent number: RE45781Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.Type: GrantFiled: February 10, 2014Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Jeffrey C. Hedrick, Kang-Wook Lee, Kelly Malone, Christy S. Tyberg