Abstract: An antenna includes a magnetic interface generator that generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna in printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to improve performance of the antenna that printed on the second layer.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.

Abstract: An antenna includes a magnetic interface generator that generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna in printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to improve performance of the antenna that printed on the second layer.

Abstract: A magnetic interface generator generates a magnetic interface at a center frequency f0. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length DAV of the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface.