Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.

Abstract: A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.

Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.

Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: A manufacturing method for a semiconductor package structure, which includes the steps of providing a circuit build-up substrate, which has a first surface that exposes multiple flip-chip bonding pads and multiple first bonding pads located around the flip-chip bonding pads; forming a conductive substrate embedded with a chip and multiple conductive pillars on the first surface of the circuit build-up substrate, in which the first surface of the chip is disposed corresponding to the flip-chip bonding pads and the second end of the conductive pillars is disposed corresponding to the first bonding pads; a second surface of the chip and a first end of each conductive pillars are exposed from an upper surface of the conductive substrates; and arranging a memory module on the conductive substrate, corresponding to the first end of the conductive pillars, wherein the memory module and the chip do not overlap in an orthographic projection direction.

Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.

Abstract: An electronic package is provided, which includes: an insulating layer; an electronic element embedded in the insulating layer and having a sensing area exposed from the insulating layer; and a circuit layer formed on the insulating layer and electrically connected to the electronic element, thereby reducing the thickness of the overall package structure.

Abstract: A semiconductor package structure includes a circuit build-up substrate, a chip, a plurality of conductive pillar, a molding layer and at least a memory module. The circuit build-up substrate has a first surface. A plurality of flip-chip bonding pads and a plurality of first bonding pads are exposed from the first surface. The chip is electrically connected to the flip-chip bonding pads. The conductive pillars are disposed on the first surface of the circuit build-up substrate and electrically connected to the first bonding pads. The molding layer is disposed on the first surface of the circuit build-up substrate to cover the chip and the conductive pillars. A second side of the chip and a first end of each conductive pillar are exposed from the molding layer. The memory module is disposed on the molding layer and electrically connected to the first end of the conductive pillar.

Abstract: An electronic package includes a circuit structure having a first electronic component disposed on one side thereof, and a second electronic component and conductive pillars disposed on the other side thereof. The second electronic component and the conductive pillars are encapsulated by an encapsulant, and end faces of the conductive pillars are exposed from the encapsulant, allowing the exposed end faces to be connected to an external circuit board. As the end faces of the conductive pillars are used as contact structures, fine-pitch electronic packages can be achieved. Also, by providing sufficient space attributed to the tall columnar structures of the conductive pillars, the second electronic component of an appropriate thickness can be obtained, allowing the electronic package to be suitable for applications requiring high voltages and/or high currents. A method for fabricating an electronic package is further provided.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device disposed in the molding compound body, the first circuit device having a first terminal at a top of the first circuit device; a first conductive via formed in the molding compound body and connected to the first terminal; a second circuit device disposed in the molding compound body, the second circuit device having a second terminal at a top of the second circuit device; a second conductive via formed in the molding compound body and connected to the second terminal; and a redistribution layer with a conductive wire formed on the molding compound body, the conductive wire connecting the first conductive via and the second conductive via; wherein the first and second terminals are respectively located at different depths of the molding compound body.

Abstract: A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.

Abstract: The disclosure provides an electronic package including an encapsulating layer, an electronic component embedded in the encapsulating layer, a plurality of conductors disposed through the encapsulating layer, and a circuit layer disposed on the encapsulating layer and electrically connected to the conductors, thereby reducing manufacturing complexity by disposing the conductors through the encapsulating layer to save costs. The disclosure further provides a method for manufacturing the electronic package as described above.

Abstract: An electronic package is provided, which includes: an insulator; an electronic element embedded in the insulator and having a sensing area exposed from the insulator; and a conductive structure disposed on the insulator and electrically connected to the electronic element, thereby reducing the thickness of the overall structure.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.

Abstract: A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.

Abstract: A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.

Abstract: A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device disposed in the molding compound body, the first circuit device having a first terminal at a top of the first circuit device; a first conductive via formed in the molding compound body and connected to the first terminal; a second circuit device disposed in the molding compound body, the second circuit device having a second terminal at a top of the second circuit device; a second conductive via formed in the molding compound body and connected to the second terminal; and a redistribution layer with a conductive wire formed on the molding compound body, the conductive wire connecting the first conductive via and the second conductive via; wherein the first and second terminals are respectively located at different depths of the molding compound body.