Abstract: A method of verifying and analyzing energy efficiency ratio (EER) of an HVAC chiller unit in accordance with the present invention provides verification and analysis of HVAC chiller units to build daily steady-state data and non-steady state data out of field dynamic EER values and provides analysis of the steady-state data, based on selected integer temperatures and tenfold load factors in the annual scale that are subject to the dynamic changes in temperatures and load factors along with chiller seasonal operation to build monthly or seasonal running EER trend, and to determine-management index values for a period of time and to determine whether energy consumption meets specified criteria, as a basis of comparison of calculations, and resulting amplitude ratios between before and after the energy-saving improvement and of totally saved energy.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Abstract: Various embodiments of the present application are directed towards a buck converter circuit including a controller circuit. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device and a source/drain terminal of the second switching device are electrically coupled. The controller is configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF. The first switching device is OFF while the second switching device is ON. The first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF.

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: Various embodiments of the present application are directed towards a buck converter circuit including a controller circuit. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device and a source/drain terminal of the second switching device are electrically coupled. The controller is configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF. The first switching device is OFF while the second switching device is ON. The first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF.

Abstract: A heat exchange system having desired anti-scaling performance and an anti-scaling method thereof are disclosed. The heat exchange system at least comprises a load control unit, a temperature and pressure detection unit and an anti-scaling treatment unit. The heat exchange system conditions bonding ways of water quality in a HVAC chiller unit, an air compressor, a heat exchanger, a cooling unit, or a boiler under a variety of scaling conditions in both field operation and water quality, by integrating the interaction of those units together with the anti-scaling method for simulating water quality that has a water quality limit same as that in field operation. The heat exchange system further integrates with a testing of anti-scaling performance to make water quality no longer charged and lose the reaction power so as to prevent scaling formation, enhance the anti-scaling performance, and ensure operating efficiency and performance.

Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.

Abstract: Devices, systems, and methods are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: Devices, systems, and methods are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.

Abstract: A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and includes first and second stages. The second stage is coupled between the first stage and the power transistor. Each of the first and second stages includes a pair of enhancement-mode high-electron-mobility transistors (HEMTs). The construction as such lowers a static current of the driving circuit.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and includes first and second stages. The second stage is coupled between the first stage and the power transistor. Each of the first and second stages includes a pair of enhancement-mode high-electron-mobility transistors (HEMTs). The construction as such lowers a static current of the driving circuit.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.