Patents by Inventor Chu-Wei Hu
Chu-Wei Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230260894Abstract: A semiconductor device includes an application processor (AP) die and a memory die directly bonded to the AP die. The memory die includes a substrate, a non-volatile memory structure on the substrate, and at least one trench capacitor in the substrate.Type: ApplicationFiled: January 16, 2023Publication date: August 17, 2023Applicant: MEDIATEK INC.Inventors: Chu-Wei Hu, Chien-Kai Huang, Tien-Yu Lu
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Patent number: 11728320Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.Type: GrantFiled: April 22, 2022Date of Patent: August 15, 2023Assignee: MEDIATEK INC.Inventors: Tien-Yu Lu, Chu-Wei Hu, Hsin-Hsin Hsiao
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Publication number: 20220246591Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Inventors: Tien-Yu LU, Chu-Wei HU, Hsin-Hsin HSIAO
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Patent number: 11342316Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.Type: GrantFiled: August 28, 2020Date of Patent: May 24, 2022Assignee: MEDIATEK INC.Inventors: Tien-Yu Lu, Chu-Wei Hu, Hsin-Hsin Hsiao
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Publication number: 20210225822Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.Type: ApplicationFiled: August 28, 2020Publication date: July 22, 2021Inventors: Tien-Yu LU, Chu-Wei HU, Hsin-Hsin HSIAO
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Patent number: 10418480Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.Type: GrantFiled: February 7, 2017Date of Patent: September 17, 2019Assignee: MediaTek Inc.Inventors: Chu-Wei Hu, Cheng Hua Lin
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Patent number: 9793337Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.Type: GrantFiled: May 27, 2016Date of Patent: October 17, 2017Assignee: MEDIATEK INC.Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
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Publication number: 20170263761Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.Type: ApplicationFiled: February 7, 2017Publication date: September 14, 2017Inventors: Chu-Wei HU, Cheng Hua LIN
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Patent number: 9508786Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.Type: GrantFiled: October 19, 2015Date of Patent: November 29, 2016Assignee: MEDIATEK INC.Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
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Publication number: 20160276338Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Yuan-Fu CHUNG, Chu-Wei HU, Yuan-Hung CHUNG
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Patent number: 9379175Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.Type: GrantFiled: December 2, 2014Date of Patent: June 28, 2016Assignee: MEDIATEK INC.Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
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Publication number: 20160043162Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Inventors: Yuan-Fu CHUNG, Chu-Wei HU, Yuan-Hung CHUNG
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Patent number: 9123558Abstract: In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.Type: GrantFiled: June 20, 2011Date of Patent: September 1, 2015Assignee: MEDIATEK INC.Inventors: Sheng-Hung Fan, Chu-Wei Hu, Chien-Chih Lin, Chih-Chung Chiu, Zheng Zeng, Wei-Li Tsao
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Publication number: 20150187757Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.Type: ApplicationFiled: December 2, 2014Publication date: July 2, 2015Inventors: Yuan-Fu CHUNG, Chu-Wei HU, Yuan-Hung CHUNG
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Patent number: 8932937Abstract: Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.Type: GrantFiled: May 20, 2002Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chu-Sheng Lee, Hsin-Chi Chen, Chu-Wei Hu
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Publication number: 20120319243Abstract: In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Inventors: Sheng-Hung Fan, Chu-Wei Hu, Chien-Chih Lin, Chih-Chung Chiu, Zheng Zeng, Wei-Li Tsao
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Patent number: 6951803Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.Type: GrantFiled: February 26, 2004Date of Patent: October 4, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai Tzeng, Cheng-Ming Wu, Chu-Wei Hu, Jung-Lieh Hsu, Kuei-Yuam Hsu
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Publication number: 20050191836Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.Type: ApplicationFiled: February 26, 2004Publication date: September 1, 2005Inventors: Kai Tzeng, Cheng-Ming Wu, Chu-Wei Hu, Jung-Lieh Hsu, Kuei-Yuam Hsu
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Patent number: 6790756Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.Type: GrantFiled: March 11, 2003Date of Patent: September 14, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chu-Wei Hu, Jiue-Wen Weng, Chung-Te Lin, So Wein Kuo
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Patent number: 6787470Abstract: A sacrificial semiconductor feature for preventing corrosion that can result during chemical-mechanical planarization (CMP) is disclosed. A semiconductor device of the invention is fabricated at least in part by performing CMP. The device includes a desired semiconductor feature and a sacrificial semiconductor feature. The desired semiconductor feature may have an unbalanced geometric pattern that includes a metallic line ending in at least one tip. The at least one tip is susceptible to corrosion resulting from performing CMP. The sacrificial semiconductor feature is preferably located off the metallic line of the desired semiconductor feature. The sacrificial semiconductor feature attracts charge induced during CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature. The presence of the sacrificial semiconductor feature thus substantially prevents corrosion of the desired semiconductor feature, including its tip(s).Type: GrantFiled: May 17, 2002Date of Patent: September 7, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chu-Wei Hu, Tsu Shih, Chen Cheng Chou