Abstract: A system and method for a solid state drive comprising a system controller and one or more extender devices coupled to the system controller is disclosed, where each extender device is coupled to a plurality of NAND storage devices and each NAND storage device comprising a plurality of NAND flash memory cells.

Abstract: A communication node is configured to automatically select an optimum common operational mode between itself and a link partner. The communication node sends advertisement packets across a fiber optic medium in order to broadcast its operational capabilities to the link partner. These operational capabilities may include 10BASE-FL and 100BASE-FL. Transitions may be inserted between the advertisement packets which may include clock pulses, data pulses and transitions. The communication node may be attached to a network having a bus architecture and may further be configured to identify an idle signal.

Abstract: A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.

Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.