Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: A method for evaluating radio performance of a device under test (DUT) comprises the following steps. A first set of points, a second set of points and a third set of points are defined to locate on a sphere surrounding the DUT. A signal power of the DUT is evaluated at the first set of points to identify a first region related to the first set of points. Candidates of the second set of points are selected based on the first region. The signal power of the DUT is evaluated at the candidates of the second set of points to identify a second region related to the second set of points. Candidates of the third set of points are selected based on the second region. The signal power of the DUT is evaluated at the candidates of the third set of points to identify a beam peak.

Abstract: A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.

Abstract: A system for extracting key phrase candidates from a corpus of documents, including a processor, a memory, and a program executing on the processor. The system is configured to run a key phrase model to extract one or more key phrase candidates from each document in the corpus and convert each extracted key phrase candidate into a feature vector. The key phrase model also filters the feature vectors to remove duplicates using a classifier that was trained on a set of key phrase pairs with manual labels indicating whether two key phrases are duplicates of each other, to produce remaining key phrase candidates. The system uses the remaining key phrase candidates in a computer-implemented application.

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.

Abstract: A packaging method and package structure for a filter chip. The packaging method includes providing a circuit substrate, covering a first surface of the circuit substrate and/or filter chip with adhesive material and forming recessed cavities or closed cavities in the adhesive material. The method further includes adhering the filter chip to the first surface of circuit substrate via the adhesive material, such that surface acoustic wave transmitting regions of the filter chip correspond to the recessed cavities or closed cavities in the adhesive material to form a gap therebetween, and encapsulating the filter chip with encapsulating material. The method further includes forming interconnecting holes extending from a second surface of the circuit substrate to pins of the filter chip, filling the interconnecting holes with conductive material, so that the conductive material is in electrical contact with a chip pin bump or pad metal of the filter chip, and forming external pin pads on the second surface.

Abstract: Disclosed are a network accuracy quantification method, system, and device, an electronic device and a readable medium, which are applicable to a many-core chip. The method includes: determining a reference accuracy according to a total core resource number of the many-core chip and the number of core resources required by each network to be quantified, with the number of the core resources required by each network to be quantified being the number of the core resources which is determined after each network to be quantified is quantified; and determining a target accuracy corresponding to each network to be quantified according to the reference accuracy and the total core resource number of the many-core chip.

Abstract: A neural network mapping method and a neural network mapping apparatus are provided. The method includes: mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of a chip; acquiring the number of phases needed by a plurality of processing elements in the chip for completing the calculation tasks, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, mapping the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the first stage of balancing.

Abstract: The present invention discloses a signal receiving apparatus having phase compensation mechanism. A first and a second receiving path of a receiving circuit perform frequency down-conversion and analog-to-digital conversion on an input signal to generate a first and a second receiving signals. The first and the second receiving paths uses a RF training signal generated by a RF training signal generation circuit as the input signal when a phase compensation is performed, and use a data signal from an antenna circuit as the input signal when a beamforming signal receiving is performed. A phase difference calculation circuit of the receiving circuit performs cross-correlation operation on the first and the second receiving signals to generate a compensation signal according to a phase difference between the first and the second receiving paths.

Abstract: Provided are a chip fine line fan-out package structure and a manufacturing method therefor. The chip fine line fan-out package structure provided and the chip fine line fan-out package structure manufactured using the manufacturing method each include an inter-chip fine winding layer and a package winding layer. The line width and line spacing of the inter-chip fine winding layer are less than the line width and line spacing of the package winding layer, and therefore, a user can choose to use different package winding layers according to actual needs. Therefore, the chip fine line fan-out package structure and the package structure manufactured using the manufacturing method can meet the use demands of users in more scenarios.

Abstract: A fan-out type package and a preparation method of the fan-out type package are provided. The fan-out type package has one or more chips having same or different functions and each having a back surface mounted in a chip mounting region of the heat dissipation sheet via the adhesive material layer, and a front surface covered by a temporary protection material; an adhesive material layer; a heat dissipation sheet; an encapsulation material layer formed by making an encapsulation material flow into and fill a gap between the temporary protection material and the heat dissipation sheet and/or cover a side of the heat dissipation sheet opposite to a side thereof mounted with the chip, and then removing the temporary protection material; a packaging circuit grown on the front surface of the chip, the encapsulation material, and the heat dissipation sheet; and a packaging circuit protection layer protecting the packaging circuit.

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

Abstract: A wireless device includes a time-sensitive queue, an access category queue, a controller, and a transmitter. The access category queue is associated with an access category and a link. The controller is coupled to the access category queue, and is used to acquire a transmission opportunity according to a set of contention parameters of the access category. The transmitter is coupled to the controller and the time-sensitive queue, and is used to when a transmission opportunity is acquired, if the time-sensitive queue contains data, generate a data frame according to the data in the time-sensitive queue, and transmit the data to another wireless device via a link.