Patents by Inventor Chuan-Jen Chang
Chuan-Jen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152326Abstract: A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.Type: ApplicationFiled: February 3, 2023Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Meng-Fan Chang, Jui-Jen Wu, Chuan-Jia Jhang
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Publication number: 20240152327Abstract: A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.Type: ApplicationFiled: February 3, 2023Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Chuan-Jia Jhang, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
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Patent number: 10923177Abstract: A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.Type: GrantFiled: December 23, 2019Date of Patent: February 16, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Jen Chang
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Patent number: 10627840Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first voltage level while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first voltage level.Type: GrantFiled: November 26, 2018Date of Patent: April 21, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Jen Chang, Hao-Huan Hsu
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Patent number: 10580477Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.Type: GrantFiled: April 5, 2018Date of Patent: March 3, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Jen Chang, Wen-Ming Lee
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Patent number: 10581420Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a difference-expanding device and a receiver. The difference-expanding device receives an input signal having voltage levels representing logical states, and converts the input signal to a processed signal by changing, based on the voltage levels, degrees in conduction of the difference-expanding device. The receiver receives the processed signal from the difference-expanding device, and determines the logical states of the input signal based on the processed signal.Type: GrantFiled: July 20, 2018Date of Patent: March 3, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Jen Chang
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Publication number: 20200028502Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a difference-expanding device and a receiver. The difference-expanding device receives an input signal having voltage levels representing logical states, and converts the input signal to a processed signal by changing, based on the voltage levels, degrees in conduction of the difference-expanding device. The receiver receives the processed signal from the difference-expanding device, and determines the logical states of the input signal based on the processed signal.Type: ApplicationFiled: July 20, 2018Publication date: January 23, 2020Inventor: CHUAN-JEN CHANG
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Publication number: 20190392890Abstract: A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.Type: ApplicationFiled: June 26, 2018Publication date: December 26, 2019Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ming Lee, Chuan-Jen Chang
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Patent number: 10515670Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.Type: GrantFiled: June 13, 2018Date of Patent: December 24, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ming Lee, Chuan-Jen Chang
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Publication number: 20190385648Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.Type: ApplicationFiled: June 13, 2018Publication date: December 19, 2019Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ming Lee, Chuan-Jen Chang
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Publication number: 20190378564Abstract: An operating method of a memory device includes the following operations: detecting a first temperature of the memory device; determining a first refresh rate according to the first temperature; and refreshing the memory array by the first refresh rate. The first refresh rate is lower than a refresh rate upper threshold.Type: ApplicationFiled: June 11, 2018Publication date: December 12, 2019Inventors: Chuan-Jen CHANG, Wen-Ming LEE
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Patent number: 10504581Abstract: A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.Type: GrantFiled: June 26, 2018Date of Patent: December 10, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ming Lee, Chuan-Jen Chang
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Patent number: 10497423Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. the computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.Type: GrantFiled: May 14, 2018Date of Patent: December 3, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Jen Chang, Wen-Ming Lee
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Publication number: 20190348101Abstract: The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: CHUAN-JEN CHANG, WEN-MING LEE
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Publication number: 20190348108Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. The computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: CHUAN-JEN CHANG, WEN-MING LEE
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Patent number: 10460790Abstract: The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.Type: GrantFiled: May 14, 2018Date of Patent: October 29, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Jen Chang, Wen-Ming Lee
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Publication number: 20190311761Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.Type: ApplicationFiled: April 5, 2018Publication date: October 10, 2019Applicant: Nanya Technology CorporationInventors: Chuan-Jen CHANG, Wen-Ming LEE
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Patent number: 10310549Abstract: An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.Type: GrantFiled: June 21, 2018Date of Patent: June 4, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Jen Chang, Wen-Ming Lee
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Publication number: 20190121379Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first degree while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first degree.Type: ApplicationFiled: November 26, 2018Publication date: April 25, 2019Inventors: Chuan-Jen CHANG, Hao-Huan HSU
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Publication number: 20190121378Abstract: A system includes a regulator, a first circuit and a first sensing circuit. The regulator is configured to provide a supply voltage, and to raise the supply voltage based on a sensing result. The first circuit is configured to operate at a first operating voltage, which is derived from the supply voltage. The first sensing circuit, independent of the regulator, is configured to provide a first sensing result by sensing the first operating voltage provided to the first circuit, wherein the first sensing result serves as a first candidate for the sensing result, wherein the first sensing circuit in space of layout is closer than the regulator to the first circuit.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Chuan-Jen CHANG, Hao-Huan HSU