Abstract: A virtual computer verification platform is provided with a verifying and debugging environment so as to develop a new microprocessor chip, a new system software, a new firmware and a new peripheral chip. The virtual computer verification platform includes a simulation system and a set of on-line debugging auxiliary tools, wherein the microprocessor chip can be designed in a Behavior model, a RTL model and a Gate model. The message communication for integrating the whole simulation system is implemented through a message passing mechanism supported by UNIX IPC (Inter-Process Communication) and PLI (Programming Language Interface) supported by Verilog.

Abstract: A buckle for a belt includes a frame having two opposite sides formed with two upwardly extending lugs each having a through hole, two arms each extending outwardly from a respective one of the lugs, and a shoulder bridging another sides of the lugs, and a retainer generally including a tubular member, a shaft, and a spring, the tubular member having an elongated opening having an edge formed at an intermediate portion thereof with a hook, each end of the tubular member having a longitudinally and outwardly extending rod member, another edge of the elongated opening having a radial groove close to an end of the tubular member, an L-shaped handle close to the radial groove, the shaft extending longitudinally through both ends of the retainer and supported by the lugs at two ends thereof, the shaft having an intermediate portion formed with a through hole, the spring having a first end engaged with the through hole of the shaft and a second end fitted in the groove, whereby the belt can be easily fastened and r

Abstract: A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each function unit in the processor is allocated for the execution of an instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots. The fixed predetermined pattern of time slots represents the resource constraints imposed on the hardware to resolve the contention for computing resources among the instruction threads. The strategy of resource allocation is exposed to a parallel compiler which organizes a sequence of instructions into the horizontal instruction words which form each thread so as to maintain the data dependencies among the instructions and to take into account the fixed predetermined allocation of hardware resources.