Abstract: A display panel and a display device are provided. The display panel includes pixel row groups, scanning driving circuits, first data lines and second data lines. One pixel row group includes first pixel rows and one pixel row includes a first pixel and a second pixel. A luminous efficiency of color light of the first pixel is lower than a luminous efficiency of color light of the second pixel. One scanning driving circuit includes a first sub scanning driving circuit and a second sub scanning driving circuit. In at least one image frame, a duration during which the first pixel is connected to the first data line for transmitting data voltage controlled by the first sub scanning driving circuit is larger than a duration during which the second pixel is connected to the second data line for transmitting data voltage controlled by the second sub scanning driving circuit.

Abstract: An apparatus, a method for fabricating the apparatus, and a method for cultivation of cells are provided. The apparatus comprises a first chamber for cultivating cells and a surface, supported in the first chamber, for cell cultivation thereon. The surface exhibits one or more fractal features, each fractal feature comprising out-of-plane fractal patterning providing non-planar microtopology for the surface.

Abstract: A time synchronization method for a time synchronization device, wherein the device is connected to a plurality of time synchronization domains through a plurality of ports, and the plurality of time synchronization domains use a plurality of PTP profiles. The method comprises determining whether each of the plurality of ports is a time receiving port or a time transmitting port; obtaining information of a grandmaster clock of the plurality of time synchronization domains; performing information conversion on the information of the grandmaster clock according to a PTP profile corresponding to each time transmitting port of the plurality of ports in the plurality of PTP profiles, so as to generate a plurality of clock information corresponding to each time transmitting port; and transmitting a corresponding clock information of the plurality of clock information to a corresponding time synchronization domain from each time transmitting port, so as to perform time synchronization.

Abstract: A method for generating an update package of software. Each installation package of the software includes multiple installation subpackages, and each installation subpackage includes multiple installation files. The method includes: obtaining first feature information and second feature information, the first feature information corresponds to the first installation subpackage, the second feature information corresponds to the second installation subpackage, the first installation subpackage is an installation subpackage in an installation package corresponding to a upgraded software version of the software, and the second installation subpackage is an installation subpackage corresponding to the first installation subpackage in an installation package corresponding to software version of the software before software upgrading; generating the update package for the software according to the first installation subpackage when the first feature information is different from the second feature information.

Abstract: A fan-out type packaging structure includes a strain adjustment layer, a plurality of chips, an encapsulation layer, a redistribution layer, and a plurality of solder balls. The strain adjustment layer is made of a polymer material and has at least 95% laser absorbance. The plurality of chips are partially embedded in the strain adjustment layer and are spaced apart from each other. The encapsulation layer surrounds the chips and is connected to the strain adjustment layer. The redistribution layer covers the encapsulation layer and the chips. The plurality of solder balls are disposed on the redistribution layer and are spaced apart from each other.

Abstract: A dual-polarized antenna, an antenna array, and a communications device are disclosed. The dual-polarized antenna includes a base board, a horizontally polarized antenna, and a vertically polarized antenna. The substrate includes a first substrate and a plurality of second substrates stacked on the first substrate. The horizontally polarized antenna includes a first radiating element disposed on the first substrate, and a first feeding unit that feeds the first radiating element. The vertically polarized unit includes a second radiating element and a second feeding unit that feeds the second radiating element. The second radiating element includes a first metal patch disposed on each second substrate. In the foregoing technical solution, the base board formed by the stacked substrates is used as a support part, so that the horizontally polarized antenna and the vertically polarized antenna are disposed on the base board, thereby reducing space occupied by the dual-polarized antenna.

Abstract: The disclosure provides a method and system for hierarchical disturbance rejection depth tracking control of an underactuated underwater vehicle, and the depth tracking of the underactuated underwater vehicle is divided into kinematic layer guidance and dynamic layer pitch tracking. Adaptive line of sight guidance is used in the kinematic layer to convert a depth error into a desired pitch angle and to estimate and compensate an angle of attack to reject disturbance introduced by an unmeasurable true angle of attack. Based on the above, in the dynamic layer, the active disturbance rejection sliding mode pitch tracking method is used to observe a composite disturbance including an unknown dynamic model and an environmental disturbance by using the active disturbance rejection framework. The model is compensated as a unified integral series type, a sliding mode control law is finally designed to resist an observation error, and a control elevator angle is calculated.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.