Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.

Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.

Abstract: A clock signal generation circuit generates a first clock signal based on second and third clock signals. The clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals. A skew reduction circuit reduces skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin of the clock signal generation circuit.

Abstract: A circuit includes a phase detector circuit, a shift register ring circuit, and a phase shift circuit. The phase detector circuit generates an indication of a phase error between a periodic signal and an input signal. The shift register ring circuit shifts stored signals through a variable number of storage circuits coupled in the shift register ring circuit. The variable number of storage circuits coupled in the shift register ring circuit is determined based on the indication of the phase error. The phase shift circuit adjusts a phase of the periodic signal based on the stored signals.

Abstract: One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.

Abstract: A clock data recovery circuit includes a phase detector circuit, a filter circuit, a parts per million (PPM) detector circuit, a PPM decoder circuit, a summation circuit, and a phase interpolator circuit. The phase detector circuit generates a phase error signal based on a periodic signal and a data signal. The filter circuit generates a filtered signal based on the phase error signal. The PPM detector circuit and the PPM decoder circuit generate control signals based on the filtered signal. The phase interpolator circuit generates the periodic signal. The clock data recovery circuit adjusts a phase of the periodic signal based on the filtered signal and the control signals in response to variations in a data rate of the data signal using spread-spectrum clocking in order to track changes in the data rate of the data signal.

Abstract: A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.