Abstract: An injection locked transmitter for an optical communication network includes a master seed laser source input substantially confined to a single longitudinal mode, an input data stream, and a laser injected modulator including at least one slave laser having a resonator frequency that is injection locked to a frequency of the single longitudinal mode of the master seed laser source. The laser injected modulator is configured to receive the master seed laser source input and the input data stream, and output a laser modulated data stream.

Abstract: The present invention provides chimeric antigen receptors (CAR) and methods of use in the treatment of diseases and disorders.

Abstract: The present application relates to a dual-polarization-joint noise processing method and device. The present application compensates the discrete spectral coefficient noise on the X polarization state with noise information carried by the discrete spectral eigenvalue on the X, Y polarization states, and a correlation coefficient between the discrete spectral eigenvalue and the discrete spectral coefficient on the X polarization state. Similarly, compensating the discrete spectral coefficient noise on the Y polarization state with noise information carried by the discrete spectral eigenvalue on the X, Y polarization states, and a correlation coefficient between the discrete spectral eigenvalue and the discrete spectral coefficient on the Y polarization state.

Abstract: The present application relates to a dual-polarization-joint noise processing method and device. The present application compensates the discrete spectral coefficient noise on the X polarization state with noise information carried by the discrete spectral eigenvalue on the X, Y polarization states, and a correlation coefficient between the discrete spectral eigenvalue and the discrete spectral coefficient on the X polarization state. Similarly, compensating the discrete spectral coefficient noise on the Y polarization state with noise information carried by the discrete spectral eigenvalue on the X, Y polarization states, and a correlation coefficient between the discrete spectral eigenvalue and the discrete spectral coefficient on the Y polarization state.

Abstract: A method for blockchain-based time stamping for digital signature is disclosed. The method includes two participants: a signer who signs a message, a verifier who verifies the message. In the method, the signer obtains hash values of a certain number of latest confirmed blocks in blockchain, binds these hash values and the message together to be a new message. The signer then generates a signature of the new message and inserts identification data of this signature and the new message into a transaction of blockchain. This method ensures that the generation time of the signature is prior to the generation time of the block which contains the signature and, at the same time, is after the generation time of the blocks whose hash values are included in the signature, which produces an accurate time interval for the digital signature.

Abstract: Obtain, at a computing device, a segment of computer code. With a classification module of a machine learning system executing on the computing device, determine a required annotation category for the segment of computer code. With an annotation generation module of the machine learning system executing on the computing device, generate a natural language annotation of the segment of computer code based on the segment of computer code and the required annotation category. Provide the natural language annotation to a user interface for display adjacent the segment of computer code.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.