Abstract: In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.

Abstract: In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.

Abstract: An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.

Abstract: In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.

Abstract: In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.

Abstract: In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.

Abstract: An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.

Abstract: In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.