Abstract: A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, an operand fetch stage, an execution stage, and a write back stage. In a first embodiment, an entire clock cycle is dedicated to the instruction fetch stage to the instruction fetch stage to retrieve instruction data from non-volatile memory in a single clock cycle. In a second embodiment, the operand fetch stage preliminarily decodes the instruction data to determine tasks to be performed to allow the execution stage to perform its time-intensive calculations in a single clock cycle. Additionally, the operand fetch stage initiates the performance of tasks determined from the decoding of the instructions to minimize the time required to perform those tasks by the execution stage.

Abstract: A system and method for efficiently handling interrupts in a microcontroller environment is disclosed. An interrupt handling circuit preserves a current state of a microcontroller comprising a plurality of primary registers for storing information relating to the current state of the microcontroller and a plurality of shadow registers coupled to at least two of the primary registers for storing the information contained in the coupled primary registers in response to receiving an interrupt enter signal from an interrupt signal generator. In one embodiment the information relating to the current state of the microcontroller includes the program counter, accumulator data, CPU status data, and an address pointer to data memory. In a preferred embodiment, the information is restored to the primary registers within one clock cycle of receiving an interrupt exit signal from the interrupt signal generator.

Abstract: A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract: A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.