Abstract: An apparatus, circuit arrangement, program product and method of scaling an image horizontally partition a source image into a plurality of partitions, with each partition having a width that is no greater than the width of a line buffer used to scale the image. By partitioning an image into a plurality of partitions, the overall width of the scaled image is not constrained by the width of the line buffer. As a result, in many instances line buffers that are significantly smaller than conventional full-width line buffers may be used to generate scaled images that are substantially wider than may be generated by conventional buffers. Moreover, when implemented in hardware, the line buffers typically occupy significantly less real estate on an integrated circuit, thus reducing both cost and power consumption.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. HDTV signals are decoded using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. The invention decodes HDTV signals using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. HDTV signals are decoded using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: An MPEG digital video decoder system, method and computer program product are presented for monitoring decoding of an encoded digital video signal for one or more predefined illegal conditions. Error detection logic is coupled to the variable length (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transformer (IDCT) and motion compensator (MC) of the decoder for detecting an illegal condition within at least one of the VLC decoder, IQ, IDCT and MC during decoding of the encoded digital video signal. The monitored illegal conditions can include a VLC/IQ control error, an IQ level overrun, and IQ/IDCT buffer error, an MC idle error and an MC macroblock start error. Error signals are reported to a central error register which is monitored periodically by the decoder's control processor. The control processor initiates recovery within the decoder system prior to stoppage of the system due to the illegal condition.

Abstract: A digital signal decoder system is provided for receiving digital video signals and processing them while reducing the external memory requirements for frame buffer storage for an MPEG-2 decoder through decimation. The system includes a motion compensation unit for processing macroblock data. The decoder portion of the decimation unit intercepts and processes the data after it has been processed by the motion compensation unit. The data is then stored in the decimate buffer before passing on to the memory control unit. From here the data is routed to the display portion of the decimation unit for further processing. At this point the data is stored in the video buffer where it then passes on to the expansion filter and then to the display. As the video data is routed through the system, it could be decimated, interpolated, reduced, expanded, or any combination of these. The decoder controller controls and synchronizes the system operation.

Abstract: A method of performing color control in a digital video decoder while minimizing memory bandwidth. A decoded color image bit map is stored in a RAM in lines corresponding to horizontal lines of pixels. Each line also has dedicated bytes for a corresponding color look up table comprising a control field and color address fields. Entries in separate preloaded color component tables are addressed by the color address fields. A transparency bit in the control field is used to select modifiers to the data in the address fields for transparency mode.

Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.