Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

Abstract: A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

Abstract: An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Abstract: The pre-driver of an output driver is calibrated so as to generate output signals having a specified duty cycle. During calibration, a closed loop is utilized to decrease the differences between the common mode voltage of the output signal and a reference voltage. Calibration data is be stored in registers so that the output driver can be readily configured for one of a plurality of signaling types, each having a respective duty cycle. Additionally, a process, voltage and temperature (PVT) detector can be utilized so that calibration of the pre-driver tracks with process, voltage and temperature variations of the integrated circuit in which the output driver resides.

Abstract: An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Abstract: The pre-driver of an output driver is calibrated so as to generate output signals having a specified duty cycle. During calibration, a closed loop is utilized to decrease the differences between the common mode voltage of the output signal and a reference voltage. Calibration data is be stored in registers so that the output driver can be readily configured for one of a plurality of signaling types, each having a respective duty cycle. Additionally, a process, voltage and temperature (PVT) detector can be utilized so that calibration of the pre-driver tracks with process, voltage and temperature variations of the integrated circuit in which the output driver resides.

Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.