Patents by Inventor Chul-ho Chung
Chul-ho Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9825033Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.Type: GrantFiled: June 29, 2016Date of Patent: November 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Oh-Kyum Kwon, Myoung-Kyu Park, Chul-Ho Chung
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Publication number: 20170289843Abstract: Disclosed are a device for transmitting a data unit and a method of operating the same. More particularly, the device of the present disclosure includes a size determination unit for determining an optimal split size for a MAC Service Data Unit (MSDU) received from an upper layer by applying a transmission time algorithm; a unit division unit for splitting the MSDU into the determined size; and a MAC layer management unit for generating plural MAC Protocol Data Units (MPDUs) based on the split plural MSDUs and the delimiter for each of the split plural MSDUs, generating an aggregate protocol data unit by applying an aggregate transmission scheme to the generated MPDUs, and delivering the generated aggregate protocol data unit to a physical layer, thus guaranteeing reliability important for video streaming and, at the same time, increasing the throughput.Type: ApplicationFiled: February 21, 2017Publication date: October 5, 2017Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI U NIVERSITYInventors: Jae Seok KIM, Eun Bi KU, Chul Ho CHUNG, Byung Cheol KANG
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Publication number: 20170040322Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.Type: ApplicationFiled: June 29, 2016Publication date: February 9, 2017Inventors: Oh-Kyum KWON, Myoung-Kyu PARK, Chul-Ho CHUNG
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Patent number: 9312184Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.Type: GrantFiled: March 7, 2014Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tea-Kwang Yu, Bae-Seong Kwon, Yong-Tae Kim, Chul-Ho Chung, Yong-Suk Choi
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Patent number: 8847355Abstract: A capacitor structure comprises a substrate extending in a horizontal direction of extension. A first gate insulating film is on the substrate and a first gate pattern is on the first gate insulating film. A first finger-shaped electrode is on the first gate pattern, and a second finger-shaped electrode is on the first gate pattern and alternately disposed with the first electrode to be spaced apart from the first electrode in the horizontal direction. The first electrode is connected to the first gate pattern, and the second electrode and the first gate pattern are insulated from each other.Type: GrantFiled: March 14, 2013Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Chul-Ho Chung
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Publication number: 20140264538Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.Type: ApplicationFiled: March 7, 2014Publication date: September 18, 2014Inventors: Tea-Kwang YU, Bae-Seong KWON, Yong-Tae KIM, Chul-Ho CHUNG, Yong-Suk CHOI
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Publication number: 20140225225Abstract: A capacitor structure comprises a substrate extending in a horizontal direction of extension. A first gate insulating film is on the substrate and a first gate pattern is on the first gate insulating film. A first finger-shaped electrode is on the first gate pattern, and a second finger-shaped electrode is on the first gate pattern and alternately disposed with the first electrode to be spaced apart from the first electrode in the horizontal direction. The first electrode is connected to the first gate pattern, and the second electrode and the first gate pattern are insulated from each other.Type: ApplicationFiled: March 14, 2013Publication date: August 14, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Chul-Ho Chung
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Patent number: 8492822Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.Type: GrantFiled: March 9, 2010Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Sung Lim, Chul-Ho Chung
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Patent number: 8493709Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.Type: GrantFiled: February 21, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Chul-Ho Chung
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Patent number: 8216860Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.Type: GrantFiled: April 8, 2011Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-hyun Jeong, Chul-ho Chung
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Publication number: 20120151726Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.Type: ApplicationFiled: February 21, 2012Publication date: June 21, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Chul-Ho CHUNG
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Patent number: 8198970Abstract: A transformer of fully symmetric structure includes a primary coil assembly and a secondary coil assembly. The primary coil assembly includes a plurality of primary coils formed in a plurality of metal layers, and a first interlayer connection unit for connecting the primary coils. The secondary coil assembly includes a plurality of secondary coils formed in the plurality of metal layers, and a second interlayer connection unit for connecting the secondary coils. The primary and secondary coils formed in the same metal layer are concentric and axisymmetric with respect to a diameter line passing through a planar center point. A balanced-unbalanced transformer (balun) is a type of transformer that may be used to convert an unbalanced signal to a balanced one or vice versa. An integrated circuit may include a semiconductor substrate and a transformer. Electrical elements such as transistors may be formed on the semiconductor substrate.Type: GrantFiled: May 12, 2009Date of Patent: June 12, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hoon Choi, Chul-Ho Chung
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Patent number: 8130483Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.Type: GrantFiled: March 17, 2010Date of Patent: March 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Chul-Ho Chung
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Publication number: 20110183441Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.Type: ApplicationFiled: April 8, 2011Publication date: July 28, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joo-hyun JEONG, Chul-ho Chung
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Patent number: 7923814Abstract: A semiconductor device includes an interlayer insulating film and an inductor. The inductor includes a first soft magnetic thin film pattern formed on the interlayer insulating film, the first soft magnetic film comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof b) at least one element selected from Ti, Hf, or B, and c) N, a metal film pattern formed on the first soft magnetic thin film pattern and a second soft magnetic thin film pattern formed on the metal film pattern, the second soft magnetic thin film pattern comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof; b) at least one element selected from Ti, Hf, or B; and c) N. Edges of the first soft magnetic thin film pattern, edges of the metal film pattern and edges of the second soft magnetic thin film pattern are vertically aligned.Type: GrantFiled: January 23, 2007Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-hyun Jeong, Chul-ho Chung
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Publication number: 20100238603Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.Type: ApplicationFiled: March 17, 2010Publication date: September 23, 2010Inventor: Chul-Ho Chung
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Publication number: 20100230381Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.Type: ApplicationFiled: March 9, 2010Publication date: September 16, 2010Inventors: Jin-Sung Lim, Chul-Ho Chung
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Publication number: 20090284339Abstract: A transformer of fully symmetric structure includes a primary coil assembly and a secondary coil assembly. The primary coil assembly includes a plurality of primary coils formed in a plurality of metal layers, and a first interlayer connection unit for connecting the primary coils. The secondary coil assembly includes a plurality of secondary coils formed in the plurality of metal layers, and a second interlayer connection unit for connecting the secondary coils. The primary and secondary coils formed in the same metal layer are concentric and axisymmetric with respect to a diameter line passing through a planar center point. A balanced-unbalanced transformer (balun) is a type of transformer that may be used to convert an unbalanced signal to a balanced one or vice versa. An integrated circuit may include a semiconductor substrate and a transformer. Electrical elements such as transistors may be formed on the semiconductor substrate.Type: ApplicationFiled: May 12, 2009Publication date: November 19, 2009Inventors: Tae-Hoon CHOI, Chul-Ho CHUNG
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Patent number: 7405643Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.Type: GrantFiled: May 17, 2007Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Hyun Jeong, Chul-Ho Chung
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Publication number: 20080174396Abstract: A transformer includes a primary coil assembly and a secondary coil assembly juxtaposed in a stack and which are electromagnetically inductively coupled and substantially symmetrical to one another. The primary coil assembly includes a plurality of primary coils coplanar with first insulation layers, respectively, and symmetrical to each other, and a first via unit connecting adjacent ones of the primary coils to each other. The secondary coil assembly includes a plurality of secondary coils coplanar with a plurality of second insulation layers, respectively, and symmetrical to each other, and a second via unit connecting adjacent ones of the secondary coils to each other.Type: ApplicationFiled: January 11, 2008Publication date: July 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Hoon CHOI, Chul-Ho CHUNG