Abstract: A guiding grid is disclosed and includes plural circumferential elements and plural radial elements. The circumferential elements are disposed concentrically relative to a central axis, spaced apart from each other in a radial direction, and form different heights relative to a bottom surface. One of the circumferential elements forms a top height relative to the bottom surface, so that the circumferential elements are divided into an outer-ring region and a central region in the radial direction. The circumferential elements located in the central region are increased in height relative to the bottom surface along the radial direction. The circumferential element located in the outer ring region are reduced in height relative to the bottom surface along the radial direction. The radial elements are connected between each of two adjacent circumferential elements. At least one of the radial elements is misaligned and discontinuous in the radial direction.

Abstract: A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: Disclosed herein is a method for determining whether a subject has or is at risk of developing colorectal cancer with an ex vivo biological sample isolated from the subject. The method comprises: determining the levels of at least two target proteins with the aid of mass spectrometry, in which the at least two target proteins are selected from the group consisting of ADAM10, CD59, and TSPAN9; and assessing whether the subject has or is at risk of developing the colorectal cancer based on the levels of the at least two target proteins. The present method may serve as a potential means for diagnosing and predicting the incidence of colorectal cancer, and the subject in need thereof could receive a suitable therapeutic regimen in time in accordance with the diagnostic results produced by the present method.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: The present disclosure provides a data storage device. The data storage device includes a first area configured to store a first data; a second area configured to store a second data. The second data is associated with the first data, and the first data and/or the second data exclude an ECC.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has an original surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor and the transistor includes a gate structure with a bottom surface under the original surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer extends beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: Methods, systems, computer program products for determining the source of activity during interaction with a user interface are provided. The method comprises selecting one or more input devices from a plurality of available input devices coupled to the user interface and receiving respective measurements for the selected one or more input devices. Based on the received respective measurements, respective feature vectors for the one or more input devices are generated and then inputted to a pre-defined regression model. Then, the source of activity is determined based on a result received from the regression model.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.

Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.

Abstract: The present application discloses a semiconductor package which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity (HTC) interconnects formed on, located between and/or placed side-by-side with the dies, a HTC substrate carrying all the dies, a HTC structural member, and a HTC heat spreader/heatsink with the dies and the HTC heat spreader thermally coupled to other HTC components in the semiconductor package. The semiconductor components can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual-or multi-sided cooling, power supply, and signaling.

Abstract: A semiconductor package is provided, which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling.