Patents by Inventor CHUN-CHE HUANG
CHUN-CHE HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163904Abstract: Methods, systems, and apparatuses are provided for sidelink resource selection or exclusion of multi-consecutive slot transmission (MCSt) in a wireless communication system to enhance and/or modify Legacy sidelink Mode 2 operation for the MCSt. A method of a first device can comprise triggering or requesting sensing-based resource selection or re-selection for performing one or more Physical Sidelink Shared Channel (PSSCH) or Physical Sidelink Control Channel (PSCCH) transmissions in a sidelink resource pool in unlicensed or shared spectrum, determining a first parameter for determining or initializing candidate multi-slot resources, receiving a Sidelink Control Information (SCI) for reserving one or more sidelink resources, selecting a number of sidelink resources from valid/identified/remaining candidate multi-slot resources after exclusion, and performing the one or more PSSCH or PSCCH transmissions on at least one of the selected number of sidelink resources.Type: ApplicationFiled: November 3, 2023Publication date: May 16, 2024Inventors: Chun-Wei Huang, Ming-Che Li, Yi-Hsuan Kung, Li-Chih Tseng
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Publication number: 20240163920Abstract: Methods, systems, and apparatuses are provided for sidelink transmission in a wireless communication system. In various embodiments, with this and other concepts, systems, and methods of the present invention, a method for a first User Equipment (UE) comprises receiving configuration for configuring two starting symbols in a Transmission Time Interval (TTI) in a sidelink resource pool, wherein a second starting symbol of the two starting symbols is later than a first starting symbol of the two starting symbols, transmitting a signaling to a second UE, wherein the signaling comprises or indicates information of a first specific (symbol) location of Sidelink (SL) Channel State Information Reference Signal (CSI-RS), and performing sidelink transmission with SL CSI-RS in the TTI to the second UE.Type: ApplicationFiled: October 20, 2023Publication date: May 16, 2024Inventors: Chun-Wei Huang, Ming-Che Li
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Patent number: 11982794Abstract: An optical photographing system includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element has an image-side surface being convex in a paraxial region thereof. The third lens element has positive refractive power. The fourth lens element has an object-side surface being concave in a paraxial region thereof. The fifth lens element with positive refractive power has two surfaces being both aspheric. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the surfaces of the sixth lens element are both aspheric, and the image-side surface of the sixth lens element includes at least one convex shape in an off-axial region thereof.Type: GrantFiled: February 22, 2023Date of Patent: May 14, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Chun-Che Hsueh, Yu-Tai Tseng, Hsin-Hsuan Huang
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Publication number: 20240121804Abstract: Methods, systems, and apparatuses can comprise a first device in a wireless communication system receiving configuration of one or more first sidelink resource pools for at least sidelink data transmission and configuration of one or more second sidelink resource pools for sidelink reference signal transmission, receiving a Downlink Control Information (DCI) for sidelink, wherein the DCI comprises a resource pool index corresponding to one sidelink resource pool, determining the DCI for scheduling sidelink data transmission or sidelink reference signal transmission based on at least the resource pool index or the one sidelink resource pool, acquiring or determining fields or information in the DCI based on the determination that the DCI is for scheduling sidelink data transmission or sidelink reference signal transmission, determining a sidelink resource based on the acquired or determined fields, or the information in the DCI, and performing a sidelink transmission on the sidelink resource in the one sidelinType: ApplicationFiled: September 27, 2023Publication date: April 11, 2024Inventors: Ming-Che Li, Chun-Wei Huang, Li-Chih Tseng
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Patent number: 11953654Abstract: An image capturing lens system includes, in order from an object side to an image side, a first lens element with positive refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof, a second lens element with negative refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, a third lens element with positive refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, and a fourth lens element with negative refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof.Type: GrantFiled: August 30, 2021Date of Patent: April 9, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Chun-Che Hsueh, Hsin-Hsuan Huang, Shu-Yun Yang
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Patent number: 11940667Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element has two surfaces being both aspheric. The fourth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, wherein two surfaces thereof are aspheric. The fifth lens element has an image-side surface being convex in a paraxial region thereof, wherein two surfaces thereof are aspheric.Type: GrantFiled: October 20, 2022Date of Patent: March 26, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Dung-Yi Hsieh, Chun-Yen Chen, Chun-Che Hsueh, Hsin-Hsuan Huang
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Patent number: 11940598Abstract: A lens system includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one of the object-side surface and the image-side surface of the first lens element has at least one inflection point. The fourth lens element has positive refractive power, the object-side surface of the fourth lens element is convex in a paraxial region thereof, and at least one of the object-side surface and the image-side surface of the fourth lens element has at least one inflection point.Type: GrantFiled: March 13, 2023Date of Patent: March 26, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Chun-Che Hsueh, Hsin-Hsuan Huang
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Patent number: 11937334Abstract: Methods, systems, and apparatuses for Sidelink Discontinuous Reception (SL DRX) in a wireless communication system to avoid ambiguity on slot offset calculations on SL DRX. A method for a UE comprises performing a SL communication associated with a destination Identity (ID), having a SL DRX configuration associated with the SL communication, wherein the SL DRX configuration comprises at least an on-duration timer and a DRX cycle, deriving a first offset associated with the SL communication based on the destination ID and the DRX cycle, deriving a second offset associated with the SL communication based on the destination ID and a number of slots per subframe, starting the on-duration timer after a time period determined based on the second offset from the beginning of a subframe, wherein the subframe is determined based on at least the first offset, and monitoring Sidelink Control Information (SCI) when the on-duration timer is running.Type: GrantFiled: March 8, 2023Date of Patent: March 19, 2024Assignee: ASUSTek Computer Inc.Inventors: Yi-Hsuan Kung, Li-Chih Tseng, Chun-Wei Huang, Ming-Che Li
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Patent number: 11924876Abstract: Methods and apparatuses for handling partial sensing and discontinuous reception for sidelink communication to reduce potential latency due to additional sensing and to improve resource utilization efficiency. Various embodiments can comprise a first device performing sidelink communication to at least a second device, or a second device in a sidelink resource pool, and triggering to perform resource selection for a sidelink data at a timing, wherein the first device (already) receives or monitors sidelink control information for a (contiguous) time duration before the timing. The first device can perform sensing for a contiguous sensing duration after the timing, determine or select a first sidelink resource from a set of sidelink resources, and perform a first sidelink transmission on the first sidelink resource for transmitting the sidelink data to the second device.Type: GrantFiled: January 11, 2022Date of Patent: March 5, 2024Assignee: ASUSTek Computer Inc.Inventors: Ming-Che Li, Chun-Wei Huang, Li-Chih Tseng
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Patent number: 10134858Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.Type: GrantFiled: April 21, 2017Date of Patent: November 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chun-Che Huang, Chia-Fu Hsu
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Publication number: 20170222003Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.Type: ApplicationFiled: April 21, 2017Publication date: August 3, 2017Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chun-Che Huang, Chia-Fu Hsu
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Patent number: 9666471Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.Type: GrantFiled: May 14, 2015Date of Patent: May 30, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chun-Che Huang, Chia-Fu Hsu
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Publication number: 20160300755Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.Type: ApplicationFiled: May 14, 2015Publication date: October 13, 2016Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chun-Che Huang, Chia-Fu Hsu
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Patent number: 9418948Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.Type: GrantFiled: September 29, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
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Patent number: 9252109Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.Type: GrantFiled: July 14, 2014Date of Patent: February 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
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Publication number: 20160020183Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.Type: ApplicationFiled: September 29, 2015Publication date: January 21, 2016Inventors: Chiang-Ming CHUANG, Chun Che HUANG, Shih-Chieh CHANG
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Patent number: 9197454Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.Type: GrantFiled: January 16, 2014Date of Patent: November 24, 2015Assignee: VIA TECHNOLOGIES, INC.Inventor: Chun-Che Huang
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Publication number: 20150200791Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: VIA TECHNOLOGIES, INC.Inventor: Chun-Che HUANG
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Publication number: 20140322908Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.Type: ApplicationFiled: July 14, 2014Publication date: October 30, 2014Inventors: Chiang-Ming CHUANG, Chun Che HUANG, Shih-Chieh CHANG
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Patent number: 8796851Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.Type: GrantFiled: January 5, 2012Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang