Patents by Inventor Chun Che Lin

Chun Che Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240169813
    Abstract: A vibrotactile device and method including an audio signal input unit, manual parameter input unit, microcontroller, vibration motor controller, and at least one vibration motor are provided. The microcontroller is coupled to the audio signal input unit and manual parameter input unit. The vibration motor controller is coupled to the microcontroller and the at least one vibration motor. At least one signal is generated by at least the audio signal input unit or the manual parameter input unit. A modulated signal is generated based, in part, on a filtered signal from the audio signal input unit and a vibration duty cycle is generated, based on a tempo value and a note value of the manual parameter input unit, to generate at least one driving parameter, respectively. The vibration motor controller drives the at least one vibration motor based on the at least one driving parameter.
    Type: Application
    Filed: November 23, 2023
    Publication date: May 23, 2024
    Inventors: Chi-Min LIN, Yao Shiao, Chun-Ta Chen, Shang che Lee, Ming Wan Lien
  • Publication number: 20240159937
    Abstract: A photographing lens assembly includes at least four lens elements that are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, at least one subsequent lens element and a last lens element that is closest to an image surface. Each of the at least four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one surface among lens surfaces from the image-side surface of the second lens element to the object-side surface of the last lens element is a metasurface having a subwavelength microstructure.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 16, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Guan-Bo LIN, Hsiang-Chi TANG, Chun-Che HSUEH, I-Hsuan CHEN
  • Publication number: 20240142664
    Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.
    Type: Application
    Filed: February 12, 2023
    Publication date: May 2, 2024
    Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
  • Publication number: 20240114683
    Abstract: A method of manufacturing a memory device includes providing a substrate and sequentially forming a stack layer and a hard mask layer on the substrate. The method includes forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from an end of the second patterned mandrels in the first direction. The method further includes using the first patterned mandrel and the second patterned mandrels as masks, patterning the hard mask layer and the stack layer sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate. A portion of the stack layer corresponding to the first mandrel is formed into the dummy structure, and a portion of the stack layer corresponding to the second patterned mandrels is formed into the word lines.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Inventors: Tsung-Wei LIN, Kun-Che WU, Chun-Yen LIAO, Chun-Sheng WU
  • Publication number: 20240101847
    Abstract: A quantum dot oil-based ink is provided. The quantum dot oil-based ink includes a quantum dot material, a dispersing solvent, a viscosity modifier, and a surface tension modifying solution. The dispersing solvent includes a linear alkane having 6 to 14 carbon atoms. The viscosity modifier includes an aromatic hydrocarbon having 10 to 18 carbon atoms or a linear olefin having 16 to 20 carbon atoms. The surface tension modifying solution includes a hydrophobic polymer material and a nonpolar solvent.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 28, 2024
    Inventors: Chun Che LIN, Chong-Ci HU, Yi-Ting TSAI, Ching-Yi CHEN, Yu-Chun LEE
  • Patent number: 11942419
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Patent number: 11879084
    Abstract: In the present disclosure embodiments, a phosphate phosphor including an activation center of trivalent chromium and a light emitting device are provided. The light emitting device includes a light source and the above mentioned phosphate phosphor, such that the phosphate phosphor is excited by the light source and emits a wide spectrum of the infrared light. The light emitting device with wide emission spectrum of the infrared light may be widely applied in detecting devices.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 23, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chun-Che Lin, Chun-Han Lu, Yi-Ting Tsai, Yu-Chun Lee, Tzong-Liang Tsai
  • Publication number: 20230108974
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 6, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Patent number: 11522001
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Publication number: 20220336348
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 11404368
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20220098482
    Abstract: In the present disclosure embodiments, a phosphate phosphor including an activation center of trivalent chromium and a light emitting device are provided. The light emitting device includes a light source and the above mentioned phosphate phosphor, such that the phosphate phosphor is excited by the light source and emits a wide spectrum of the infrared light. The light emitting device with wide emission spectrum of the infrared light may be widely applied in detecting devices.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 31, 2022
    Inventors: Chun-Che LIN, Chun-Han LU, Yi-Ting TSAI, Yu-Chun LEE, Tzong-Liang TSAI
  • Patent number: 11257953
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 11219115
    Abstract: An extreme ultra-violet (EUV) lithography system includes an EUV source and EUV scanner. A droplet generator provides a droplet stream in the EUV source. A gas shield is configured to surround the droplet stream. When a laser reacts a droplet in the stream EUV radiation and ionized particles are produced. The gas shield can reduce contamination resulting from the ionized particles by conveying the ionized particles to a droplet catcher. Components of the EUV source may be biased with a voltage to repel or attract ionized particles to reduce contamination from the ionized particles.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Wu, Tzung-Chi Fu, Chun Che Lin, Po-Chung Cheng, Huai-Tei Yang
  • Patent number: 11004973
    Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
  • Patent number: 10998415
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 10957545
    Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin
  • Publication number: 20210083048
    Abstract: A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming LIN, Shiu-Ko JANGJIAN, Chun-Che LIN, Ying-Lang WANG, Wei-Ken LIN, Chuan-Pu LIU
  • Publication number: 20210043670
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN