Patents by Inventor Chun Chen

Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT HAVING TRANSISTORS WITH DIFFERENT WIDTH SOURCE AND DRAIN TERMINALS
    Publication number: 20240088147
    Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Inventors: XinYong WANG, Cun Cun CHEN, Ying HUANG, Chih-Liang CHEN, Li-Chun TIEN
  • PROCESSING ELEMENT ARRAY AND OPERATING METHOD THEREOF
    Publication number: 20240086358
    Abstract: A processing element array includes N processing elements (PE) arranged linearly, N?2, and an operating method of the PE array includes: performing a first data transmission procedure, where an initial value of I is 1 and the first data transmission procedure includes: operating, by an ith PE, according to a first datum stored in itself, and sending the first datum to other PEs for their operations, adding 1 to I when I<N, and performing the first data transmission procedure again, performing a second data transmission procedure when I is equal to N, which includes: operating, by the Jth PE, according to a second datum stored in itself, and sending the second datum to other PEs for their operations, reducing J by 1 when J>1 and the (J?1)th PE has the second datum, and performing the second data transmission procedure again.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 14, 2024
    Inventors: Yu-Sheng Lin, Trista Pei-Chun CHEN, Wei-Chao CHEN
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • A METHOD OF, AN ELECTRONIC SENSING DEVICE AND A SYSTEM FOR PROCESSING AN INTERFERENCE DETECTED BY A FIRST ELECTRONIC SENSING DEVICE
    Publication number: 20240085520
    Abstract: A method of processing an interference detected by a first microwave sensor is disclosed. The method comprising the steps of: receiving, by a second microwave sensor, from the first microwave sensor a message comprising a signal feature profile representing the interference detected by the first microwave sensor; matching, by the second microwave sensor, the signal feature profile comprised in the received message with a stored feature profile, the stored feature profile obtained by the second microwave sensor from its own received signal, and determining, by the second microwave sensor, that the interference detected by the first microwave sensor is caused by the second microwave sensor, if the signal feature profile matches the stored feature profile.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 14, 2024
    Inventors: CHUN YANG, JIALONG QIU, ZHIQUAN CHEN, GANG WANG
  • SEMICONDUCTOR DEVICE INCLUDING DEEP VIAS
    Publication number: 20240088024
    Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Ta-Pen GUO, Chien-Ying CHEN, Li-Chun TIEN, Lee-Chung LU
  • 3D PRINTER EXTRUSION STRUCTURE
    Publication number: 20240083111
    Abstract: A 3D printer extrusion structure, comprising: a housing; a motor provided on the housing; an active extrusion gear provided in the housing and connected to the motor; an adjusting support rotatably connected inside the housing; a driven extrusion gear provided at one end of the adjusting support and rotatably connected to the adjusting support; and an elastic member, the elastic member being connected to an other end of the adjusting support to enable the end of the adjusting support provided with the driven extrusion gear to approach the active extrusion gear, so that the driven extrusion gear works in conjunction with the active extrusion gear to extrude material, wherein the end of the adjusting support provided with the driven extrusion gear extends to the outside of the housing.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Huilin LIU, Jingke TANG, Chun CHEN, Danjun AO, Dajiang WU
  • LOGIC CELL STRUCTURE AND INTEGRATED CIRCUIT WITH THE LOGIC CELL STRUCTURE
    Publication number: 20240088899
    Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: SHAO-HUAN WANG, CHUN-CHEN CHEN, SHENG-HSIUNG CHEN, KUO-NAN YANG
  • INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT
    Publication number: 20240086609
    Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 14, 2024
    Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
  • HYBRID CUT METAL GATE TO ACHIEVE MINIMUM CELL PITCHES, REDUCING ROUTING AND RISING THE YIELD
    Publication number: 20240088030
    Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Liang CHEN, Chi-Yu LU, Ching-Wei TSAI, Chun-Yuan CHEN, Li-Chun TIEN
  • INTEGRATED CIRCUIT FIN STRUCTURE
    Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • ELECTRONIC DEVICE WIRELESS CONNECTIONS
    Publication number: 20240090053
    Abstract: In one example in accordance with the present disclosure, an electronic device is described. The electronic device includes a wireless controller. The wireless controller is to establish a first wireless connection between the electronic device and a peripheral device to receive a unique identifier for a second electronic device. The wireless controller is also to establish, based on the unique identifier for the second electronic device, a second wireless connection between the electronic device and the second electronic device. The electronic device includes a wireless transceiver to wirelessly transfer data to the second electronic device through the second wireless connection.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 14, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chung-Chun Chen, Chen-Hui Lin, Chih-Ming Huang, Ming-Shien Tsai
  • ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES
    Publication number: 20240090310
    Abstract: A compound comprising a first ligand LA of Formula I, is provided. In Formula I, moiety A is a 5-membered or 6-membered ring; moiety B is a fused ring structure comprising at least four rings; K is a direct bond, O, or S; each of Z1 and Z2 is independently C or N; each RA and RB is independently hydrogen or a General Substituent; at least one RB comprises a cyclic group or an electron-withdrawing group; LA is coordinated to a metal M that has an atomic mass of at least 40 and is optionally coordinated to other ligands; and the ligand LA is optionally linked with other ligands. Formulations, OLEDs, and consumer products including the compound are also provided.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 14, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi TSAI, Alexey Borisovich DYATKIN, Walter YEAGER, Pierre-Luc T. BOUDREAULT, Hsiao-Fan CHEN, Wei-Chun SHIH
  • SEMICONDUCTOR DEVICE PACKAGE, ELECTRONIC ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240088001
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
  • Integrated circuit and manufacturing method thereof
    Patent number: 11929361
    Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 12, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xin-Yong Wang, Li-Chun Tien, Chih-Liang Chen
  • Integrated fan-out package
    Patent number: 11929333
    Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Liquid crystal polymer film and laminate comprising the same
    Patent number: 11926698
    Abstract: Provided are a liquid crystal polymer film (LCP film) and a laminate comprising the same. The LCP film has a first surface and a second surface opposite each other, and the first surface has an arithmetical mean height of a surface (Sa) less than 0.32 ?m. The LCP film with proper Sa is suitable to be stacked with a metal foil, such that a laminate comprising the LCP film can have an advantage of low insertion loss.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 12, 2024
    Assignee: CHANG CHUN PLASTICS CO., LTD.
    Inventors: An-Pang Tu, Chia-Hung Wu, Chien-Chun Chen
  • LLC Resonant Converter with Windings Fabricated on PCB
    Publication number: 20240079965
    Abstract: An LLC resonant converter includes a switching circuit for converting a DC voltage into switching signal, a resonant tank coupled to the switching circuit to receive the switching signal and to provide a primary current, a transformer circuit coupled to the resonant tank. The transformer circuit includes a plurality of separated transformers, each has a primary side and a secondary side windings disposed on the PCB, where the primary side winding of each transformer can be selected to couple in series or in parallel with the primary side winding of other transformers to form a dynamically varied equivalent primary side winding, maintaining the turns ratio to fine-tune the resonant tank. The gain curve of the LLC converter can be adjusted by electrically coupling an external excitation inductor, a resonant capacitor or a resonant inductor to the resonant tank, according to the demand of output current.
    Type: Application
    Filed: October 15, 2022
    Publication date: March 7, 2024
    Inventors: Chun-Chen Chen, Jian-Hsieng Lee, Yao-Chun Tung
  • SELF-TUNING MODEL COMPRESSION METHODOLOGY FOR RECONFIGURING DEEP NEURAL NETWORK AND ELECTRONIC DEVICE
    Publication number: 20240078432
    Abstract: A self-tuning model compression methodology for reconfiguring a Deep Neural Network (DNN) includes: receiving a pre-trained DNN model and a data set; performing an inter-layer sparsity analysis to generate a first sparsity result; and performing an intra-layer sparsity analysis to generate a second sparsity result, including: defining a plurality of sparsity metrics for the network; performing forward and backward passes to collect data corresponding to the sparsity metrics; using the collected data to calculate values for the defined sparsity metrics; and visualizing the calculated values using at least a histogram.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Applicant: Kneron Inc.
    Inventors: JIE WU, JUNJIE SU, BIKE XIE, Chun-Chen Liu
  • DETECTION SYSTEM AND METHOD FOR THE MIGRATING CELL
    Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES
    Publication number: 20240076307
    Abstract: Provided are compounds of Formula Ir(LA)x(LC)y wherein: ligand LA has Formula I? ?and ligand LC has Formula II?
    Type: Application
    Filed: October 10, 2023
    Publication date: March 7, 2024
    Applicant: Universal Display Corporation
    Inventors: Wei-Chun SHIH, Zhiqiang JI, Pierre-Luc T. BOUDREAULT, Hsiao-Fan CHEN, Tongxiang LU