Patents by Inventor Chun-Cheng Tsao
Chun-Cheng Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8173948Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.Type: GrantFiled: October 20, 2009Date of Patent: May 8, 2012Assignee: DCG Systems, Inc.Inventor: Chun-Cheng Tsao
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Patent number: 7884024Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.Type: GrantFiled: May 29, 2007Date of Patent: February 8, 2011Assignee: DCG Systems, Inc.Inventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore R. Lundquist, Rajesh Kumar Jain
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Patent number: 7697146Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.Type: GrantFiled: February 24, 2006Date of Patent: April 13, 2010Assignee: DCG Systems, Inc.Inventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore R. Lundquist
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Publication number: 20100038555Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.Type: ApplicationFiled: October 20, 2009Publication date: February 18, 2010Applicant: DCG SYSTEMS, INC.Inventor: Chun-Cheng TSAO
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Patent number: 7612321Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.Type: GrantFiled: September 8, 2005Date of Patent: November 3, 2009Assignee: DCG Systems, Inc.Inventor: Chun-Cheng Tsao
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Patent number: 7439168Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.Type: GrantFiled: October 12, 2004Date of Patent: October 21, 2008Assignee: DCG Systems, IncInventors: Christian Boit, Theodore R. Lundquist, Chun-Cheng Tsao, Uwe Jürgen Kerst, Stephan Schoemann, Peter Sadewater
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Publication number: 20070293052Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.Type: ApplicationFiled: May 29, 2007Publication date: December 20, 2007Applicant: Credence Systems CorporationInventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore Lundquist, Rajesh Jain
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Patent number: 7245133Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.Type: GrantFiled: November 9, 2004Date of Patent: July 17, 2007Assignee: Credence Systems CorporationInventors: Chun-Cheng Tsao, Eugene Delenia
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Publication number: 20060188797Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.Type: ApplicationFiled: February 24, 2006Publication date: August 24, 2006Applicant: Credence Systems CorporationInventors: Erwan Roy, Chun-Cheng Tsao, Theodore Lundquist
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Patent number: 7036109Abstract: Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.Type: GrantFiled: October 17, 2002Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Chun-Cheng Tsao, Theodore R. Lundquist, William Thompson, Erwan Le Roy, Eugene A. Delenia
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Publication number: 20060079086Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.Type: ApplicationFiled: October 12, 2004Publication date: April 13, 2006Applicant: Credence Systems CorporationInventors: Christian Boit, Theodore Lundquist, Chun-Cheng Tsao, Uwe Kerst, Stephan Schoemann, Peter Sadewater
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Publication number: 20060076503Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.Type: ApplicationFiled: September 8, 2005Publication date: April 13, 2006Applicant: Credence Systems CorporationInventor: Chun-Cheng Tsao
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Publication number: 20060012385Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.Type: ApplicationFiled: November 9, 2004Publication date: January 19, 2006Inventors: Chun-Cheng Tsao, Eugene Delenia
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Method and apparatus for determining thickness of a semiconductor substrate at the floor of a trench
Publication number: 20050236583Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using a FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool.Type: ApplicationFiled: April 19, 2005Publication date: October 27, 2005Inventors: Erwan Roy, Chun-Cheng Tsao -
Patent number: 6955930Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool.Type: GrantFiled: May 30, 2002Date of Patent: October 18, 2005Assignee: Credence Systems CorporationInventors: Erwan Le Roy, Chun-Cheng Tsao
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Method and apparatus for global die thinning and polishing of flip-chip packaged integrated circuits
Patent number: 6939209Abstract: A reliable, inexpensive “back side” thinning process and apparatus therefor, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.Type: GrantFiled: October 24, 2003Date of Patent: September 6, 2005Assignee: Credence Systems CorporationInventors: Chun-Cheng Tsao, John Valliant -
Patent number: 6872581Abstract: Methods for integrated circuit diagnosis, characterization or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an integrated circuit is thinned to about 1 to 3 ?m from the deepest well, a voltage is applied to a circuit element that is beneath the outer surface of the thinned substrate. The applied voltage induces an electrical potential on the outer surface, which is detected as a surface feature on the outer surface by its interaction with the charged particle beam.Type: GrantFiled: April 15, 2002Date of Patent: March 29, 2005Assignee: NPTest, Inc.Inventors: Christopher Shaw, Chun-Cheng Tsao, Theodore R. Lundquist
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Method and apparatus for global die thinning and polishing of flip-chip packaged integrated circuits
Publication number: 20040106358Abstract: A reliable, inexpensive “back side” thinning process and apparatus therefor, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.Type: ApplicationFiled: October 24, 2003Publication date: June 3, 2004Inventors: Chun-Cheng Tsao, John Valliant -
Publication number: 20040014401Abstract: A reliable, inexpensive “back side” thinning process, capable of globally as well as locally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip or wire-bond packaged die is mounted on a thinning/polishing tool with the backside accessible. The thinning/polishing tool can be a lapping machine used for global thinning, or a mini milling machine, laser, FIB, or E-beam machine for local thinning. The thickness of the die is measured at at least five locations on the die before thinning. The thinning tool removes silicon on the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy.Type: ApplicationFiled: April 23, 2003Publication date: January 22, 2004Inventors: Chun-Cheng Tsao, John Valliant, Theodore R. Lundquist
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Patent number: 6672947Abstract: A reliable, inexpensive “back side” thinning process, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.Type: GrantFiled: August 7, 2001Date of Patent: January 6, 2004Assignee: NPTEST, LLCInventors: Chun-Cheng Tsao, John Valliant