Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.

Abstract: A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

Abstract: An isolated bispecific antibody or antigen-binding portion thereof includes a first chain which specifically binds to human PD-1(hPD-1) and blocks the interaction between hPD-1 and PD-L1, and a second chain which specifically binds to human CD47 and inhibits its interaction with SIRP-alpha, where the first chain and the second chain are coupled in a knob-in-hole format through their respective CH3 domain.

Abstract: A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.

Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.

Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.

Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.

Abstract: A heat dissipation device includes a housing, a heat dissipation plate, a first fan and at least two second fans. The housing has a first sidewall and a second sidewall that are opposite to each other. The first sidewall has a first opening area and the second sidewall has a second opening area which is facing the first opening area. The heat dissipation plate is located inside the housing and covers at least one heat source. An opening that corresponds to the first opening area and contains the first fan penetrates through the heat dissipation plate. Each of the at least two second fans that include airflow exits facing away from the first fan is located nearby the heat dissipation plate. The housing includes side surfaces that connect the first sidewall and the second sidewall and have three side opening areas that are facing different directions.

Abstract: A heat dissipation device includes a housing, a heat dissipation plate, a first fan and at least two second fans. The housing has a first sidewall and a second sidewall that are opposite to each other. The first sidewall has a first opening area. The second sidewall has a second opening area. The first opening area and the second opening area are facing each other. The heat dissipation plate is located inside the housing and covers at least one heat source. An opening penetrates through the heat dissipation plate, and the opening corresponds to the first opening area. The first fan is located inside the opening. The at least two second fans are located nearby the heat dissipation plate. The at least two second fans are facing a first direction. The housing further includes side surfaces that connect the first sidewall and the second sidewall.

Abstract: A last extension for a shoe last provides a pattern defining an origin location. The origin location on the last extension can be used to identify locations or points on a last or a shoe component on a last for control of location-critical manufacturing operations, including decorative and functional operations.

Abstract: A last extension for a shoe last provides a pattern defining an origin location. The origin location on the last extension can be used to identify locations or points on a last or a shoe component on a last for control of location-critical manufacturing operations, including decorative and functional operations.

Abstract: An electronic device includes a base, a circuit board and a heat dissipating module. The base includes a bottom cover and a frame. The frame is disposed on the bottom cover. An accommodating space is between the bottom cover and the frame. The bottom cover has an air inlet. The circuit board is disposed in the accommodating space. The circuit board has a through hole. The through hole corresponds to the air inlet. The heat dissipating module is disposed in the accommodating space and located above the circuit board. The heat dissipating module includes a fan. The fan corresponds to the through hole. The fan drives airflow to flow into the accommodating space from the air inlet and the through hole along an axial direction of the fan and then flow out of the base from the accommodating space along the axial direction of the fan.