Patents by Inventor Chun-Chi Yu
Chun-Chi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10643685Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.Type: GrantFiled: November 1, 2018Date of Patent: May 5, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Gerchih Chou, Chih-Wei Chang, Shen-Kuo Huang
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Patent number: 10630289Abstract: An ODT circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first and second ODTs are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third and the fourth ODTs are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.Type: GrantFiled: March 1, 2019Date of Patent: April 21, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Shen-Kuo Huang, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou
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Patent number: 10522204Abstract: A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.Type: GrantFiled: November 7, 2018Date of Patent: December 31, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Fu-Chin Tsai, Shih-Han Lin, Chih-Wei Chang, Gerchih Chou
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Patent number: 10269443Abstract: A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.Type: GrantFiled: February 12, 2018Date of Patent: April 23, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
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Patent number: 10056124Abstract: A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.Type: GrantFiled: December 14, 2016Date of Patent: August 21, 2018Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang, Gerchih Chou
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Publication number: 20180233211Abstract: A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.Type: ApplicationFiled: February 12, 2018Publication date: August 16, 2018Inventors: Chun-Chi YU, Chih-Wei CHANG, Shen-Kuo HUANG
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Publication number: 20180166109Abstract: A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang, Gerchih Chou
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Patent number: 9653404Abstract: The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction.Type: GrantFiled: August 23, 2016Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Jing Wang, En-Chiuan Liou, Mei-Chen Chen, Han-Lin Zeng, Chia-Hung Lin, Chun-Chi Yu
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Patent number: 9570130Abstract: A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.Type: GrantFiled: April 8, 2016Date of Patent: February 14, 2017Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Fu-Chin Tsai, Shih-Chang Chen
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Patent number: 9494873Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.Type: GrantFiled: August 28, 2014Date of Patent: November 15, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: En-Chiuan Liou, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20160329085Abstract: A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.Type: ApplicationFiled: April 8, 2016Publication date: November 10, 2016Inventors: Chun-Chi YU, Chih-Wei CHANG, Gerchih CHOU, Fu-Chin TSAI, Shih-Chang CHEN
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Patent number: 9482964Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.Type: GrantFiled: May 15, 2014Date of Patent: November 1, 2016Assignee: United Microelectronics CorpInventors: En-Chiuan Liou, Chia-Chang Hsu, Yi-Ting Chen, Teng-Chin Kuo, Chun-Chi Yu
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Patent number: 9448471Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.Type: GrantFiled: July 21, 2014Date of Patent: September 20, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 9400435Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.Type: GrantFiled: August 12, 2014Date of Patent: July 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chia-Chang Hsu, Teng-Chin Kuo, Chia-Hung Wang, Tuan-Yen Yu, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 9355708Abstract: A memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.Type: GrantFiled: March 17, 2015Date of Patent: May 31, 2016Assignee: Realtek Semiconductor Corp.Inventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
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Publication number: 20160103396Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.Type: ApplicationFiled: October 13, 2014Publication date: April 14, 2016Inventors: En-Chiuan Liou, Teng-Chin Kuo, Chun-Chi Yu
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Publication number: 20160035411Abstract: a memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.Type: ApplicationFiled: March 17, 2015Publication date: February 4, 2016Inventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
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Publication number: 20160018728Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Inventors: En-Chiuan Liou, Yu-Cheng Tung, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20160018741Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.Type: ApplicationFiled: August 28, 2014Publication date: January 21, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: EN-CHIUAN LIOU, TENG-CHIN KUO, YUAN-CHI PAI, CHUN-CHI YU
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Publication number: 20150362905Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.Type: ApplicationFiled: August 12, 2014Publication date: December 17, 2015Inventors: En-Chiuan Liou, Chia-Chang Hsu, Teng-Chin Kuo, Chia-Hung Wang, Tuan-Yen Yu, Yuan-Chi Pai, Chun-Chi Yu