Patents by Inventor Chun-Chieh Chan
Chun-Chieh Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11239092Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.Type: GrantFiled: April 27, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
-
Publication number: 20220014649Abstract: A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.Type: ApplicationFiled: May 27, 2021Publication date: January 13, 2022Inventors: Ying-Hsin Lin, Wen-Hsia Kung, Chun-Chieh Chan
-
Patent number: 11223749Abstract: A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.Type: GrantFiled: May 27, 2021Date of Patent: January 11, 2022Assignee: Realtek Semiconductor Corp.Inventors: Ying-Hsin Lin, Wen-Hsia Kung, Chun-Chieh Chan
-
Publication number: 20210409642Abstract: The present invention discloses a signal enhancement relay apparatus is provided. A display data channel stretching circuit includes a direct and an indirect channels. A snooper circuit is disposed at the direct channel. The indirect channel includes a master and a slave paths having a master and a slave transmission circuits disposed thereon. The direct channel is selected under a default passive mode such that a snooper link bridging handler circuit is enabled to monitor a display data transmission on the direct path through the snooper circuit, to perform a channel link bridging process corresponding to a data enhancement transmission channel accordingly.Type: ApplicationFiled: May 7, 2021Publication date: December 30, 2021Inventors: CHUN-CHIEH CHAN, CHIA-HAO CHANG, TAI-JUNG WU, MING-AN WU
-
Patent number: 11183347Abstract: A keyboard includes a base plate, a hook structure, and a plastic engaging member. The base plate has a top surface. The hook structure is connected to the base plate and raised relative to the top surface. The plastic engaging member is located on the top surface and fixed to at least a part of the hook structure.Type: GrantFiled: January 9, 2020Date of Patent: November 23, 2021Assignee: Chicony Electronics Co., Ltd.Inventors: Chao-Chin Hsieh, Chun-Chieh Chan
-
Patent number: 11137971Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral āiā is a positive integer.Type: GrantFiled: October 29, 2020Date of Patent: October 5, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ying-Ying Song, Chien-Hsun Lu, Yi-Han Peng, Chun-Chieh Chan
-
Publication number: 20210208838Abstract: A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral āiā is a positive integer.Type: ApplicationFiled: October 29, 2020Publication date: July 8, 2021Inventors: YING-YING SONG, CHIEN-HSUN LU, YI-HAN PENG, CHUN-CHIEH CHAN
-
Publication number: 20210185291Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.Type: ApplicationFiled: December 14, 2020Publication date: June 17, 2021Inventors: CHUN-CHIEH CHAN, TAI-JUNG WU, MING-AN WU, CHIEN-HSUN LU
-
Publication number: 20210132641Abstract: A dynamic voltage compensation circuit suitable for performing voltage compensation between an electronic device and a multimedia device, and includes a current detection unit, a calculation module and a voltage output unit. The current detection unit is configured to obtain the output current of the electronic device outputting the multimedia device from the bus power terminal. The calculation module is configured to receive the output current and an ideal reference voltage, execute a voltage compensation algorithm to calculate a predetermined output voltage based on the output current, the ideal reference voltage, and a compensation coefficient, and generate a control signal according to the predetermined output voltage. The voltage output unit is configured to receive a control signal, and is controlled by the control signal to generate a compensated output voltage and output it to a bus power terminal.Type: ApplicationFiled: July 3, 2020Publication date: May 6, 2021Inventors: Chun-Chieh CHAN, Hsing-Yu LIN, Yi-Cheng LIN
-
Publication number: 20210133136Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port.Type: ApplicationFiled: July 7, 2020Publication date: May 6, 2021Inventors: CHUN-CHIEH CHAN, WEI-LUN HUANG, CHIA-LUNG HUNG, YUNG-MING LIN
-
Patent number: 10991523Abstract: A keyboard device includes a base plate and a plurality of keyswitches disposed on the base plate. At least one of the keyswitches includes a keycap, two linkages, and two magnetic attraction members. The linkages are connected between the base plate and the keycap and configured to guide the movements of the keycap toward and away from the base plate. The magnetic attraction members are rotatably connected to the linkages, respectively, and are configured to attract each other. When the magnetic attraction members abut against each other, the keycap is at a highest position relative to the base plate. When the keycap moves toward the base plate from the highest position, the magnetic attraction members are separated from each other.Type: GrantFiled: December 25, 2018Date of Patent: April 27, 2021Assignee: Chicony Electronics Co, , Ltd.Inventors: Shin-Chin Weng, Chun-Chieh Chan, Chao-Chin Hsieh, Chih-Feng Chen
-
Publication number: 20200402742Abstract: A keyboard includes a base plate, a hook structure, and a plastic engaging member. The base plate has a top surface. The hook structure is connected to the base plate and raised relative to the top surface. The plastic engaging member is located on the top surface and fixed to at least a part of the hook structure.Type: ApplicationFiled: January 9, 2020Publication date: December 24, 2020Inventors: Chao-Chin HSIEH, Chun-Chieh CHAN
-
Publication number: 20200258758Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
-
Patent number: 10636673Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The method includes performing a first planarization process over the second layer until the stop layer is exposed. The method includes performing an etching process to remove the second layer, the stop layer, and an upper portion of the first layer. The method includes performing a second planarization process over the first layer.Type: GrantFiled: July 5, 2018Date of Patent: April 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
-
Publication number: 20200035426Abstract: A keyboard device includes a base plate and a plurality of keyswitches disposed on the base plate. At least one of the keyswitches includes a keycap, two linkages, and two magnetic attraction members. The linkages are connected between the base plate and the keycap and configured to guide the movements of the keycap toward and away from the base plate. The magnetic attraction members are rotatably connected to the linkages, respectively, and are configured to attract each other. When the magnetic attraction members abut against each other, the keycap is at a highest position relative to the base plate. When the keycap moves toward the base plate from the highest position, the magnetic attraction members are separated from each other.Type: ApplicationFiled: December 25, 2018Publication date: January 30, 2020Inventors: Shin-Chin WENG, Chun-Chieh CHAN, Chao-Chin HSIEH, Chih-Feng CHEN
-
Publication number: 20190152016Abstract: A chemical mechanical polishing apparatus is provided. The chemical mechanical polishing apparatus includes a polishing pad, a pad conditioner, a measurement tool, and a controller. The polishing pad is provided in a processing chamber for polishing a wafer placed on the polishing surface of the polishing pad. The pad conditioner is configured to condition the polishing surface. The measurement tool is provided in the processing chamber and configured to measure the downward force of the pad conditioner. The controller is coupled to the pad conditioner and the measurement tool, and is configured to adjust the downward force of the pad conditioner in response to an input from the measurement tool.Type: ApplicationFiled: February 26, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chen WEI, Jheng-Si SU, Shih-Ho LIN, Jen-Chieh LAI, Chun-Chieh CHAN
-
Publication number: 20190096693Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The method includes performing a first planarization process over the second layer until the stop layer is exposed. The method includes performing an etching process to remove the second layer, the stop layer, and an upper portion of the first layer. The method includes performing a second planarization process over the first layer.Type: ApplicationFiled: July 5, 2018Publication date: March 28, 2019Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
-
Publication number: 20190006204Abstract: Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Yu-Chen WEI, Chun-Jui CHU, Chun-Chieh CHAN, Jen-Chieh LAI, Shih-Ho LIN
-
Patent number: 10170343Abstract: Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.Type: GrantFiled: June 30, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chen Wei, Chun-Jui Chu, Chun-Chieh Chan, Jen-Chieh Lai, Shih-Ho Lin
-
Patent number: 9642546Abstract: The present invention proposes a relaxation state evaluation system and method and a computer program product thereof. The method comprises steps: measuring ECG data of a user; analyzing the ECG data to generate a first, second, third and fourth parameters, wherein the first parameter is the short-scale entropy slope of the user before cardiovascular disease treatment (CVDT); the second parameter is the difference of the post-CVDT and pre-CVDT mean RR intervals; the third parameter is the logarithm of the variance of the pre-CVDT high frequency NN intervals; the fourth parameter is the logarithm of the ratio of the variances of the pre-CVDT low frequency and high frequency NN intervals; working out an evaluation index, which is a function of the abovementioned parameters; and evaluating the relaxation state of the user, wherein the user is determined to be in a relaxation state if the evaluation index is over a threshold.Type: GrantFiled: March 11, 2015Date of Patent: May 9, 2017Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Hung-Chih Chiu, Yi-Lwun Ho, Yen-Hung Lin, Hsi-Pin Ma, Tzung-Dau Wang, Chun-Chieh Chan, Hung-Chun Lu