Abstract: A two dimensional touch sensor panel can be thermoformed or curved by another process to a three-dimensional touch sensor panel, and the three-dimensional touch sensor panel can be laminated to a three-dimension surface having a highly curved or spherical shape. In some examples, thermoforming a two-dimensional touch sensor panel into a three-dimensional touch sensor panel can result in strain of the touch electrodes, and can result in non-uniform three-dimensional touch electrodes (distortion of the two-dimensional touch electrode pattern). The strain can be a function of the curved touch-sensitive surface and/or process related mechanical strain from thermoforming. In some examples, a three-dimensional touch sensor panel can be formed with uniform area touch electrodes using a two-dimensional touch sensor panel pattern with non-uniform area touch electrodes in accordance with the strain pattern expected for a given curved surface and thermoforming technique.

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation, the selectively exposed photoresist layer is developed to form a pattern in the photoresist layer. The photoresist composition includes a polymer including monomer units with photocleaving promoters, wherein the photocleaving promoters are one or more selected from the group consisting of living free radical polymerization chain transfer agents, electron withdrawing groups, bulky two dimensional (2-D) or three dimensional (3-D) organic groups, N-(acyloxy)phthalimides, and electron stimulated radical generators.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. The forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.

Abstract: A detection device for detecting an eyeball includes a frame element, a transceiver, and a contact lens element. The transceiver is disposed on the frame element. The transceiver transmits a first RF (Radio Frequency) signal. The contact lens element includes a resonator. The resonator converts the first RF signal into a first ultrasonic signal. The first ultrasonic signal is transmitted to the eyeball. The resonator converts a second ultrasonic signal from the eyeball into a second RF signal. The transceiver receives the second RF signal.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.

Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: In a method of manufacturing a semiconductor device, a metallic photoresist layer is formed over a target layer to be patterned, the metallic photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern. The metallic photo resist layer is an alloy layer of two or more metal elements, and the selective exposure changes a phase of the alloy layer.

Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.

Abstract: An electronic device has sensors. More particularly, the electronic device is a small form factor electronic device such as earbuds, styluses, or electronic pencils, earphones, and so on. In some implementations, one or more touch sensors and one or more force sensors are coupled to a flexible circuit. In various implementations, the touch sensor and the force sensor are part of a single module controlled by a single controller. In a number of implementations, the flexible circuit is laminated to one or more portions of an interior surface of the electronic device.

Abstract: An electronic device may have a display, a display cover layer, and an image transport layer formed from a coherent fiber bundle. The coherent fiber bundle may have an input surface that receives an image from the display and a corresponding output surface to which the image is provide through the coherent fiber bundle. The coherent fiber bundle may be placed between the display and the display cover layer and mounted to a housing. The coherent fiber bundle may have fiber cores with bends that help conceal the housing from view and make the display appear borderless. A central portion of the coherent fiber bundle may be formed from different materials and/or structures than a surrounding border portion of the layer.

Abstract: A two dimensional touch sensor panel can be thermoformed or curved by another process to a three-dimensional touch sensor panel, and the three-dimensional touch sensor panel can be laminated to a three-dimension surface having a highly curved or spherical shape. In some examples, thermoforming a two-dimensional touch sensor panel into a three-dimensional touch sensor panel can result in strain of the touch electrodes, and can result in non-uniform three-dimensional touch electrodes (distortion of the two-dimensional touch electrode pattern). The strain can be a function of the curved touch-sensitive surface and/or process related mechanical strain from thermoforming. In some examples, a three-dimensional touch sensor panel can be formed with uniform area touch electrodes using a two-dimensional touch sensor panel pattern with non-uniform area touch electrodes in accordance with the strain pattern expected for a given curved surface and thermoforming technique.

Abstract: The present disclosure provide a light emitting device package, including a light emitting die emitting a first color and an encapsulant encapsulating the light emitting die. The encapsulant includes a matrix and a plurality of inert particles dispersed in the matrix. The inert particles are transparent to the first color, and a radiation pattern of the light emitting package is lambertian-like.

Abstract: The present disclosure involves a light-emitting diode (LED) packaging structure. The LED packaging structure includes a submount having a substrate and a plurality of bond pads on the substrate. The LED packaging structure includes a plurality of p-type LEDs bonded to the substrate through a first subset of the bond pads. The LED packaging structure includes a plurality of n-type LEDs bonded to the substrate through a second subset of the bond pads. Some of the bond pads belong to both the first subset and the second subset of the bond pads. The p-type LEDs and the n-type LEDs are arranged as alternating pairs. The LED packaging structure includes a plurality of transparent and conductive components each disposed over and electrically interconnecting one of the pairs of the p-type and n-type LEDs. The LED packaging structure includes one or more lenses disposed over the n-type LEDs and the p-type LEDs.

Abstract: The invention provides methods for rapidly synthesizing heteroatom containing zeolites including Sn-Beta, Si-Beta, Ti-Beta, Zr-Beta and Fe-Beta. The methods for synthesizing heteroatom zeolites include using well-crystalline zeolite crystals as seeds and using a fluoride-free, caustic medium in a seeded dry-gel conversion method. The Beta zeolite catalysts made by the methods of the invention catalyze both isomerization and dehydration reactions.