Patents by Inventor Chun Chung Su
Chun Chung Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990488Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.Type: GrantFiled: March 12, 2021Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
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Patent number: 11979971Abstract: An extreme ultra violet (EUV) radiation source apparatus includes a collector mirror, a target droplet generator for generating a tin (Sn) droplet, a rotatable debris collection device, one or more coils for generating an inductively coupled plasma (ICP), a gas inlet for providing a source gas for the ICP, and a chamber enclosing at least the collector mirror and the rotatable debris collection device. The gas inlet and the one or more coils are configured such that the ICP is spaced apart from the collector mirror.Type: GrantFiled: April 10, 2019Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Shuo Su, Chun-Lin Chang, Han-Lung Chang, Li-Jui Chen, Po-Chung Cheng
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240090210Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
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Patent number: 11856761Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.Type: GrantFiled: September 16, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
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Publication number: 20230246026Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Inventors: Chih-Ching WANG, Chun-Chung SU, Chung-Wei WU, Jon-Hsu HO, Kuan-Lun CHENG, Wen-Hsing HSIEH, Wen-Yuan CHEN, Zhi-Qiang WU
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Patent number: 11626400Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.Type: GrantFiled: July 16, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ching Wang, Wen-Yuan Chen, Chun Chung Su, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20230020933Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: Chih-Ching WANG, Wen-Yuan CHEN, Chun-Chung SU, Jon-Hsu HO, Wen-Hsing HSIEH, Kuan-Lun CHENG, Chung-Wei WU, Zhiqiang WU
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Publication number: 20220359546Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.Type: ApplicationFiled: September 16, 2021Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
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Publication number: 20220359545Abstract: A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a plurality of second nanostructures extending along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls. The semiconductor device includes a second gate structure straddling the plurality of second nanostructures.Type: ApplicationFiled: September 13, 2021Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Chih-Ching Wang
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Patent number: 8927362Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.Type: GrantFiled: January 31, 2014Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su
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Publication number: 20140141582Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.Type: ApplicationFiled: January 31, 2014Publication date: May 22, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su
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Patent number: 8680576Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.Type: GrantFiled: May 16, 2012Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su
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Patent number: 8633516Abstract: The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.Type: GrantFiled: September 28, 2012Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Gwan Sin Chang, Kuo-Cheng Ching, Chun Chung Su, Shi Ning Ju
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Publication number: 20130307021Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su