Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Abstract: At least one alternating stack of insulating layers and silicon nitride layers is formed over a substrate. Memory stack structures are formed through the at least one alternating stack. A trench and an etch mask spacer are formed such that the trench extends through the entirety of the alternating stack while the etch mask covers upper layers of the at least one alternating stack. Lower silicon nitride layers are removed employing a first hot phosphoric acid wet etch process. After removal of the etch mask spacer, upper silicon nitride layers are removed employing a second hot phosphoric acid wet etch process. Electrically conductive layers are formed in the lateral recesses formed by removal of the silicon nitride layers.

Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A label-free biosensor detection arrangement incorporating an external cavity laser (ECL) includes a tunable lasing element (e.g. an antireflection coated laser diode or semiconductor optical amplifier) and a narrow bandwidth resonant reflectance filter as the wavelength-selective element for the tunable lasing element. A sample is deposited on the surface of the resonant reflectance filter containing a biological material. The wavelength emitted by the external cavity laser is continuously tunable by binding interactions between the biological material and the resonant reflectance filter or adsorption of the biological material present in the sample on resonant reflectance filter. The narrow bandwidth resonance reflectance filter can take the form of photonic crystal (PC), a Bragg stack, or a Brag fiber reflection filter.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.