Abstract: Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.

Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Abstract: A process is described for the manufacture of a capacitor having low V.sub.cc. Said process is fully compatible with standard IC manufacturing and introduces minimum modification thereto. The process involves the formation of a capacitor having both upper and lower electrodes that comprise layers of a metal silicide. The lower electrode is formed as a byproduct of the SALICIDE process while the upper electrode is formed by first laying down a layer of polysilicon followed by a layer of a silicide-forming metal such as titanium, cobalt, or tungsten. Sufficient of the metal must be provided to ensure that all of the polysilicon gets transformed to silicide.

Abstract: A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.