Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.

Abstract: A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

Abstract: A memory cell of a charge-trapping non-volatile memory is provided. The memory cell is formed on a well region of a semiconductor substrate. The memory cell includes a storage transistor. A gate structure of the storage transistor includes a first tunneling layer, a second tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with a surface of the well region. The second tunneling layer covers the first tunneling layer. The trapping layer covers the second tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer. The second tunneling layer has gradient nitrogen distribution. A first nitrogen concentration of a first region of the second tunneling layer close to the first tunneling layer is lower than a second nitrogen concentration of a second region of the second tunneling layer close to the trapping layer.

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

Abstract: An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate.

Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate.

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.