Patents by Inventor Chun-Hsien Lin
Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152187Abstract: A foldable electronic device including a first body, a second body, a hinge module, and a cover is provided. The hinge module is connected to the first body and the second body, such that the first body and the second body are rotated relatively to be folded or unfolded via the hinge module. The hinge module has a protruding rod eccentric to a rotation center of the hinge module. The cover is pivoted to the second body and located on a moving path of the protruding rod. The hinge module drives the cover to be rotated relative to the second body via the protruding rod.Type: ApplicationFiled: October 24, 2023Publication date: May 9, 2024Applicant: Acer IncorporatedInventors: Chun-Hung Wen, Chun-Hsien Chen, Hui-Ping Sun, Wen-Neng Liao, Yu-Ming Lin, Kuan-Lin Chen
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Patent number: 11978511Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.Type: GrantFiled: January 21, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
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Patent number: 11978678Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.Type: GrantFiled: August 5, 2022Date of Patent: May 7, 2024Assignee: INNOLUX CORPORATIONInventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
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Publication number: 20240144862Abstract: An electronic device with a first region and a second region located around the first region is disclosed. The electronic device includes a first gate driver and a second gate driver disposed in the second region, and a first transistor and a second transistor disposed in the first region. The first gate driver is used for outputting a first signal. The second gate driver is used for outputting a second signal. The first transistor is used for receiving the first signal from the first gate driver. The second transistor is used for receiving the second signal from the second gate driver. In a top view of the electronic device, the first region has a first side and a second side opposite to the first side, and the first gate driver and the second gate driver are located more adjacent to the first side and away from the second side.Type: ApplicationFiled: January 3, 2024Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Chun-Hsien LIN, Jui-Feng KO, Geng-Fu CHANG
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Patent number: 11973117Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.Type: GrantFiled: August 3, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
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Publication number: 20240134470Abstract: An electronic device includes a first insulating layer, a first conductive portion, a second conductive portion, a transistor, and an electronic unit. The first insulating layer has a first opening penetrating the first insulating layer along a first direction. The first conductive portion is disposed in the first opening. The second conductive portion is electrically connected to the first conductive portion. The transistor is electrically connected to the second conductive portion. The electronic unit is electrically connected to the first conductive portion. In a cross-sectional view of the electronic device, the electronic unit and the second conductive portion are disposed on two opposite sides of the first insulating layer respectively, the first conductive portion has a first length along a second direction perpendicular to the first direction, the second conductive portion has a second length along the second direction, and the first length is different from the second length.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Applicant: InnoLux CorporationInventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
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Patent number: 11955579Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.Type: GrantFiled: April 21, 2022Date of Patent: April 9, 2024Assignee: INNOLUX CORPORATIONInventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
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Publication number: 20240113010Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.Type: ApplicationFiled: September 20, 2023Publication date: April 4, 2024Inventors: Po-Hsien Huang, Yu-Huei Lee, Hsin-Hung Lin, Chun-Yuan Shih, Lien-Chieh Yu
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Patent number: 11948278Abstract: An image quality improvement method and an image processing apparatus using the same are provided. Denoising filtering is performed to an original image by a filter to obtain a preliminary processing image. The preliminary processing image is input to a multi-stage convolutional network model to generate an optimization image through the multi-stage convolutional network model. The multi-stage convolutional network model includes multiple convolutional network sub-models, and these convolutional network sub-models respectively correspond to different network architectures.Type: GrantFiled: August 18, 2021Date of Patent: April 2, 2024Assignee: National Chengchi UniversityInventors: Yan-Tsung Peng, Sha-Wo Huang, Ming-Hao Lin, Chin-Hsien Wu, Chun-Lin Tang
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Patent number: 11949040Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.Type: GrantFiled: April 21, 2022Date of Patent: April 2, 2024Assignee: INNOLUX CORPORATIONInventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
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Publication number: 20240096907Abstract: An electronic device is provided. The electronic device includes a substrate, an electronic unit, and a circuit layer. The substrate has a first surface and a second surface, and the second surface is opposite the first surface. The electronic unit is disposed on the first surface. The circuit layer is disposed on the second surface. The circuit layer includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings are used to transmit a first signal. The plurality of second wirings are used to transmit a second signal. Moreover, a width of one of the plurality of second wirings is different from a width of one of the plurality of first wirings.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventor: Chun-Hsien LIN
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Publication number: 20240098932Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.Type: ApplicationFiled: July 19, 2023Publication date: March 21, 2024Applicant: Acer IncorporatedInventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
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Patent number: 11935728Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.Type: GrantFiled: January 5, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Cheng Wu, Sheng-Ying Wu, Ming-Hsien Lin, Chun Fu Chen
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Publication number: 20240074329Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Sheng-Yuan Hsueh
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Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 11914804Abstract: A touch display device is provided in this disclosure. The touch display device includes a substrate, a first conductive layer, a second conductive layer, a stacked structure, an inorganic light emitting unit, and a touch sensing circuit. The first conductive layer is disposed on the substrate. The first conductive layer includes a gate electrode. The second conductive layer is disposed on the first conductive layer. The second conductive layer includes a source electrode and a drain electrode. The stacked structure is disposed on the substrate. The stacked structure includes a conductive channel and a sensing electrode. The inorganic light emitting unit is disposed on the stacked structure. The inorganic light emitting unit is electrically connected with the drain electrode via the conductive channel. The touch sensing circuit is electrically connected with the sensing electrode.Type: GrantFiled: March 10, 2022Date of Patent: February 27, 2024Assignee: InnoLux CorporationInventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
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Publication number: 20240062713Abstract: An electronic device includes a substrate, a transistor, a first conductive portion, a first power input portion and a first wire. The substrate includes a first surface, a second surface opposite to the first surface, and a side surface located between the first surface and the second surface. The transistor is disposed on the first surface. The first conductive portion is disposed on the side surface and electrically connected to the transistor. The first power input portion and the first wire are disposed on the second surface. The first power input portion is electrically connected to the first conductive portion through the first wire. The first wire includes a first segment, a second segment and a third segment. An extension direction of the first segment, an extension direction of the second segment, and an extension direction of the third segment are not parallel to each other.Type: ApplicationFiled: October 27, 2023Publication date: February 22, 2024Applicant: Innolux CorporationInventor: Chun-Hsien Lin
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Patent number: 11908395Abstract: An electronic device including a panel, a Chip on Film and a flexible circuit board is disclosed. The panel includes a first gate driver, a switch transistor and a driving transistor. An output terminal of the switch transistor is coupled to a control terminal of the driving transistor. The first gate driver is used for receiving an AC signal and a DC signal and outputting a control signal to a control terminal of the switch transistor. The Chip on Film is electrically connected to the panel and used for transmitting a data signal to an input terminal of the switch transistor and transmitting the AC signal to the first gate driver. The flexible circuit board is electrically connected to the panel and used for transmitting a power signal to an input terminal of the driving transistor and transmitting the DC signal to the first gate driver.Type: GrantFiled: February 8, 2023Date of Patent: February 20, 2024Assignee: InnoLux CorporationInventors: Chun-Hsien Lin, Jui-Feng Ko, Geng-Fu Chang
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Patent number: 11869900Abstract: An electronic device is provided. The electronic device includes a substrate, a light-emitting unit, and a circuit layer. The substrate has a first surface and a second surface, and the second surface is opposite the first surface. The light-emitting unit is disposed on the first surface, and the circuit layer is disposed on the second surface. The circuit layer includes a first layer and a second layer. The second layer is disposed on the first layer. The first layer includes a plurality of first wirings. The second layer includes a plurality of second wirings. The plurality of first wirings intersect with the plurality of second wirings.Type: GrantFiled: September 16, 2021Date of Patent: January 9, 2024Assignee: INNOLUX CORPORATIONInventor: Chun-Hsien Lin
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Publication number: 20240006468Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.Type: ApplicationFiled: July 28, 2022Publication date: January 4, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang