Patents by Inventor Chun-Hsing Su
Chun-Hsing Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090210Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
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Patent number: 9847269Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.Type: GrantFiled: July 31, 2015Date of Patent: December 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao
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Publication number: 20170033063Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao
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Patent number: 9358660Abstract: A grinding wheel includes a base disk, and a plurality of teeth protruding beyond a surface of the base disk. The plurality of teeth is aligned to an elongated ring encircling a center of the grinding wheel.Type: GrantFiled: May 29, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsing Su, Jing-Cheng Lin, Tsei-Chung Fu, Wen-Hua Chang, Yi-Chao Mao
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Patent number: 9337063Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: GrantFiled: July 3, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20150258657Abstract: A grinding wheel includes a base disk, and a plurality of teeth protruding beyond a surface of the base disk. The plurality of teeth is aligned to an elongated ring encircling a center of the grinding wheel.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Inventors: Chun-Hsing Su, Jing-Cheng Lin, Tsei-Chung Fu, Wen-Hua Chang, Yi-Chao Mao
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Publication number: 20140322866Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8772929Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: GrantFiled: November 16, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Patent number: 8629043Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: GrantFiled: November 16, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Publication number: 20130119533Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20130122689Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Publication number: 20120052630Abstract: A method for manufacturing a chip package includes exposing a ground ring out of encapsulating material in a direct or indirect way and forming a conductive film electrically connected to the ground ring so as to form an EMI shield and prevent external EMI. The present invention also massively forms conductive film for package structure for lowering the complexity and cost of manufacturing processes.Type: ApplicationFiled: March 23, 2011Publication date: March 1, 2012Inventors: Chang-Chih LIN, Shou-Chian Hsu, Kuo-Yu Yeh, Chun-Hsing Su