Abstract: A semiconductor structure is received that has a first and second fins. A first epitaxial feature is formed on the first fin and has a first type dopant. A first capping layer is formed over the first epitaxial feature. A second epitaxial feature is formed on the second fin and has a second type dopant different from the first type dopant. A first metal is deposited on the second epitaxial feature and on the first capping layer. A first silicide layer is formed from the first metal and the second epitaxial feature, and a second capping layer is formed from the first metal and the first capping layer. The second capping layer is selectively removed. A second metal is deposited on the first epitaxial feature and over the second epitaxial feature. A second silicide layer is formed from the second metal and the first epitaxial feature.

Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.

Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the epitaxial S/D feature, the silicide layer is disposed on sidewalls of the epitaxial S/D feature, a dielectric layer disposed over sidewalls of the silicide layer, and an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.