Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.

Abstract: The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

Abstract: The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.

Abstract: A portable electronic device includes a cover, a main body, a first bracket, a second bracket and a rotary shaft. The main body includes a top surface, a bottom surface opposite to the top surface, and a guiding groove disposed on the top surface. One end of the first bracket pivots to the cover, and the other of the first bracket is slidable in the guiding groove. One end of the second bracket pivots to the cover. The rotary shaft pivots to the other of the second bracket and the main body to allow the second bracket to rotate about an axis of rotation relative to the main body. An orthographic projection of the guiding groove on the bottom surface of the main body and an orthographic projection of the rotary shaft on the bottom surface of the main body are overlapped with each other.

Abstract: An electronic device including a first body, a second body, a linking member, a plurality of keys, and an actuating module is provided. The first body has a display surface and the second body is adapted to be connected to the first body. The linking member is disposed within the second body. The keys are movably connected to the second body. The actuating module is disposed within the second body and located between the linking member and the keys. The linking member moves via a relative movement between the first body and the second body, so that the actuating module pushes the keys to move from the inside of the second body to the outside of the second body.

Abstract: A portable electronic device adapted to be detachably connected to a cradle having a containing cavity is provided, wherein an inner wall of the containing cavity has a recess. The portable electronic device includes a body and a locking-and-releasing mechanism disposed in the body and including a driving unit and a latch. The driving unit is disposed in the body. The latch is connected to the driving unit and suitable for being driven by the driving unit to protrude out of the body or hide in the body. When the portable electronic device is disposed in the containing cavity, the driving unit drives the latch to protrude out of the body and be engaged with the recess. When the portable electronic device is going to be detached from the containing cavity, the driving unit drives the latch to be disengaged from the recess and move back in the body.

Abstract: An electronic device including a first body, an input module and a functional element is provided. The input module is movably disposed on the first body and adapted to be moved between a first position and a second position. The functional element is disposed on the input module. When the input module is located at the first position, the functional element is concealed in the first body. When the input module is located at the second position, the functional element is exposed outside the first body.

Abstract: A portable electronic device includes a cover, a main body, a first bracket, a second bracket and a rotary shaft. The main body includes a top surface, a bottom surface opposite to the top surface, and a guiding groove disposed on the top surface. One end of the first bracket pivots to the cover, and the other of the first bracket is slidable in the guiding groove. One end of the second bracket pivots to the cover. The rotary shaft pivots to the other of the second bracket and the main body to allow the second bracket to rotate about an axis of rotation relative to the main body. An orthographic projection of the guiding groove on the bottom surface of the main body and an orthographic projection of the rotary shaft on the bottom surface of the main body are overlapped with each other.

Abstract: An electronic device includes a first body and a second body. The first body includes a first main body and a first magnetic element fixed in the first main body. The second body includes a second main body, a supporting unit, a second magnetic element, and a third magnetic element. The second main body is adapted to hold the first body. The supporting unit is pivoted to the second main body. The second magnetic element is fixed in the second main body. The third magnetic element is slidably configured in the second main body to restrict a rotation of the supporting unit relative to the second main body. When the first body leans against the second main body, the third magnetic element is subject to a magnetic attraction force from the first magnetic element and escapes from the supporting unit, so that the supporting unit supports the first body.

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.