Abstract: A wireless voice box not restricted to a one-to-one BLUETOOTH communication mode but able to connect to a variety of devices within a certain proximity comprises a micro controller unit and a radio frequency device, the micro controller unit and the radio frequency device can be communicatively connected to each other.

Abstract: A device for inputting commands includes a casing, a rotatable disk, and a processor. The rotatable disk can rotate relative to the casing, and has a plurality of input modes. The rotatable disk includes a switch button for switching among the input modes. The rotatable disk further includes a pointer. The casing includes an annular area surrounding the rotatable disk. The annular area has a plurality of input positions. The input positions correspond to characters of one character set corresponding to the current input mode. The processor is received in the casing, and can generate a command or control signal according to a character corresponding to an input position when the pointer is aligned with the input position.

Abstract: A wireless joint includes a converter, a radio frequency (RF) device, and a connector. The converter realizes a conversion between an audio signal and a wireless signal. The RF device receives and transmits the wireless signal. The connector connects with a microphone body.

Abstract: An analyzing method and an analyzing system for graphics process are provided. The analyzing method includes the following steps. A graphics application program is provided and a plurality of graphics parameters of the graphics application program are obtained. The graphics application program is classified to be at least one of a plurality of groups according to the graphics parameters. A plurality weighting coefficients are obtained. A total loading of a graphics processing unit for performing the graphics application program is calculated according to the weighting coefficients and the graphics parameters.

Abstract: Systems and methods for reducing trapped electrons within a NAND string are described. During a sensing operation, one or more control circuits may discharge or initiate discharge of control gates corresponding with contiguous memory cell transistors of a NAND string from a read pass voltage (e.g., 10V) to a second voltage less than the pass voltage (e.g., 2V) in an order starting from a first set of the contiguous memory cell transistors closest to the first end of the NAND string and ending with a second set of the contiguous memory cell transistors closest to the second end of the NAND string. Subsequently, the one or more control circuits may either concurrently or simultaneously discharge the control gates corresponding with the contiguous memory cell transistors from the second voltage to a third voltage less than the intermediate voltage (e.g., from 2V to 0V).

Abstract: A wireless joint includes a converter, a radio frequency (RF) device, and a connector. The converter realizes a conversion between an audio signal and a wireless signal. The RF device receives and transmits the wireless signal. The connector connects with a microphone body.

Abstract: A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.

Abstract: An analyzing method and an analyzing system for graphics process are provided. The analyzing method includes the following steps. A graphics application program is provided and a plurality of graphics parameters of the graphics application program are obtained. The graphics application program is classified to be at least one of a plurality of groups according to the graphics parameters. A plurality weighting coefficients are obtained. A total loading of a graphics processing unit for performing the graphics application program is calculated according to the weighting coefficients and the graphics parameters.

Abstract: A cache memory includes a tag memory array and a data memory array. A control register records a reconfiguration status of at least one cache way, a start address of the tag memory array, and a start address of the data memory array. A memory controller is electrically connected to the tag memory array, the data memory array, and the control register. The memory controller controls a data access state of the tag memory array according to the mode byte and the tag base address. The memory controller controls a data access state of the data memory array according to the mode byte and the data base address. A selection module is electrically connected between the tag memory array, the data memory array, and the memory controller. The cache memory solves the problem of idle tag memory of the tag memory array.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: A cache memory includes a tag memory array and a data memory array. A control register records a reconfiguration status of at least one cache way, a start address of the tag memory array, and a start address of the data memory array. A memory controller is electrically connected to the tag memory array, the data memory array, and the control register. The memory controller controls a data access state of the tag memory array according to the mode byte and the tag base address. The memory controller controls a data access state of the data memory array according to the mode byte and the data base address. A selection module is electrically connected between the tag memory array, the data memory array, and the memory controller. The cache memory solves the problem of idle tag memory of the tag memory array.

Abstract: A processor capable of storing trace data is disclosed. The processor includes a core adapted to execute programs, as well as a cache memory electrically connected to the core. The cache memory includes a core way and a trace way. The core way is adapted to store data that is required when the core executes the programs. The trace way is adapted to store data that is generated during debugging operations of the core. A control method of the processor is also disclosed.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.

Abstract: Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

Abstract: Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.

Abstract: A processor capable of storing trace data is disclosed. The processor includes a core adapted to execute programs, as well as a cache memory electrically connected to the core. The cache memory includes a core way and a trace way. The core way is adapted to store data that is required when the core executes the programs. The trace way is adapted to store data that is generated during debugging operations of the core. A control method of the processor is also disclosed.

Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.