Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.

Abstract: A method for manufacturing shallow trench isolation (STI) structures in semiconductor device manufacturing including a method for minimizing divot formation in a shallow trench isolation process is disclosed. A trench liner oxide is deposited and then removed and recessions adjacent a trench are formed to be replaced by an etching resistant layer which covers the recessions to form a protective collar over the trench opening corners.

Abstract: The present invention discloses a method of forming self-aligned unlanded via holes. First, a substrate having a patterned conductive layer on its surface is provided, and then a first dielectric layer is deposited on the substrate by using high density plasma chemical vapor deposition (HDP CVD). Next, a silicon nitride layer and a second dielectric layer are sequentially deposited on the first dielectric layer. Thereafter, the second dielectric layer, the silicon nitride layer and the first dielectric layer are etched back to remove a portion of the silicon nitride layer overlying the patterned conductive layer. Finally, a third dielectric layer is deposited, and then via holes are defined in the third dielectric layer.

Abstract: A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while retaining a plurality of sacrificial via pillars, and removing portions of the conducting layer under the removed sacrificial layer; (c) forming a first insulating layer between the plurality of the sacrificial via pillars, and then planarizing the first insulating layer to expose tops of the plurality of sacrificial via pillars; and (d) removing the plurality of the sacrificial via pillars while retaining the first insulating layer to form the plurality of the self-aligned via holes. By the above-described method, the formed via holes are self-aligned to the underlying metal lines and pads and less photolithography equipment requirement is needed to define fine via holes.

Abstract: A method for manufacturing a metal-oxide-semico nductor field effect transistor (MOSFET) having a drain and a source each of which has a lightly doped area, an enhanced lightly doped area and a heavily doped area is disclosed.

Abstract: This invention discloses a memory cell having a first polysilicon as a gate. The memory cell includes a three-layer structure covering the first polysilicon as gate with a plurality of via-1 openings exposing the first polysilicon as gate therein wherein the three-layer structure includes a first TEOS oxide layer covered by a silicon nitride layer which is covered by a second TEOS oxide layer. The second TEOS layer includes a resistor portion defined a plurality of trenches therein. The memory cell further includes a patterned second polysilicon layer covered the via-1 openings thus contacting the gate and a connector portion on the second TEOS layer to function as connector therefor. The second polysilicon layer further covering the resistor portion includes the plurality of trenches to function as a load resistor therein whereby the load resistor is prolonged by the trenches.

Abstract: This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings.

Abstract: A method of semiconductor fabrication that reduces an antenna effect that can occur during a plasma etching procedure. The semiconductor device has circuitry fabricated over the surface of a silicon substrate and includes a gate structure having a gate oxide layer beneath a conductor layer. The method includes etching a polysilicon layer formed over the surface of the circuitry. The method also includes forming trenches in the polysilicon layer at the roots of sidewalls of gate structures of the semiconductor device, at an early stage of plasma etching, before the polysilicon layer has been completely consumed. The plasma may include a gas mixture of chlorine and oxygen. The gas mixture may have a chlorine/oxygen flow ratio of about 100/5 sccm.