Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: A DMA system includes at lease one read bus, at least one write bus, at least one buffer memory bus, and a DMA controller. The DMA controller comprises a plurality of channels and a bus arbiter. The channels are electrically connected to the read bus, the write bus, and the buffer memory bus. A source address and a destination address of data for each channel are assigned by a control table. The bus arbiter performs bus arbitration and prioritizes data access among the read bus, the write bus, and the buffer memory bus.

Abstract: A DMA system includes at lease one read bus, at least one write bus, at least one buffer memory bus, and a DMA controller. The DMA controller comprises a plurality of channels and a bus arbiter. The channels are electrically connected to the read bus, the write bus, and the buffer memory bus. A source address and a destination address of data for each channel are assigned by a control table. The bus arbiter performs bus arbitration and prioritizes data access among the read bus, the write bus, and the buffer memory bus.

Abstract: A method and an apparatus analogically output low-resolution digital signals to achieve an equal analog output result of a high-resolution digital signal under a request of signal quality. The low-resolution digital signals are compensatively output multiple times to gain the energy thereof equal to the energy output by the high-resolution digital signal. Therefore, a digital-to-analog conversion with fewer bits satisfies a higher demand for accuracy generally achieved by a digital-to-analog conversion with more bits.

Abstract: A method and an apparatus analogically output low-resolution digital signals to achieve an equal analog output result of a high-resolution digital signal under a request of signal quality. The low-resolution digital signals are compensatively output multiple times to gain the energy thereof equal to the energy output by the high-resolution digital signal. Therefore, a digital-to-analog conversion with fewer bits satisfies a higher demand for accuracy generally achieved by a digital-to-analog conversion with more bits.