Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A computer system consists of a plurality of electronic elements and a switch control circuit. The switch control circuit controls the computer system to enter a stand-by/power off state from a normal state when the computer system receives a stand-by/power off command under the normal state, and stops outputting a stand-by power having at least one stand-by voltage level to at least one part of electronic elements among the plurality of electronic elements. At this time, the computer system has entered a simulated mechanical off state from the stand-by/power off state. A number of electronic elements supplied by the stand-by power when the computer system lies under the simulated mechanical off state is smaller than a number of electronic elements supplied by the stand-by power when the computer system lies under the stand-by/power off state.

Abstract: A controlling circuit for controlling an operating clock of a logic circuit in an electronic device and the method thereof are disclosed. The controlling circuit includes a storage device, a detector, at least one comparator, and a controller. The storage device stores a first threshold value and a first return value. The detector detects a system load of the electronic device to generate a detection value. The comparator compares the detection value with the first threshold value or the first return value. When the detection value decreases to reach the first threshold value, the comparator generates a first indication signal. When the detection value increase to reach the first return value, the comparator generates a second indication signal. The controller enables underclocking of the logic circuit when receiving the first indication signal, and disables underclocking of the logic circuit when receiving the second indication signal.

Abstract: A controlling circuit for controlling an operating clock of a logic circuit in an electronic device and the method thereof are disclosed. The controlling circuit includes a storage device, a detector, at least one comparator, and a controller. The storage device stores a first threshold value and a first return value. The detector detects a system load of the electronic device to generate a detection value. The comparator compares the detection value with the first threshold value or the first return value. When the detection value decreases to reach the first threshold value, the comparator generates a first indication signal. When the detection value increase to reach the first return value, the comparator generates a second indication signal. The controller enables underclocking of the logic circuit when receiving the first indication signal, and disables underclocking of the logic circuit when receiving the second indication signal.

Abstract: A method for detecting a power load of a power supply module, includes: receiving a pulse width modulation (PWM) signal generated by the power supply module, wherein the PWM signal is utilized for controlling a driving voltage outputted from the power supply module; detecting a duty cycle of the PWM signal; and determining the power load of the power supply module according to the duty cycle.

Abstract: A method for detecting a power load of a power supply module, includes: receiving a pulse width modulation (PWM) signal generated by the power supply module, wherein the PWM signal is utilized for controlling a driving voltage outputted from the power supply module; detecting a duty cycle of the PWM signal; and determining the power load of the power supply module according to the duty cycle.