Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A deflecting plate includes a silicon-on-insulator (SOI) substrate. The SOI substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.

Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.

Abstract: A method for forming a photomask includes the following steps. A first target pattern is provided, wherein the first target pattern includes a first pattern area and a second pattern area. The first pattern area includes a block pattern. The second pattern area includes multiple stripe patterns. A first sidewall reset area is defined in the second pattern area. A retarget procedure is executed on the first target pattern to obtain a second target pattern. The photomask is formed based on the second target pattern.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Abstract: A semiconductor image sensor includes a pixel. The pixel includes a first substrate; and a photodiode in the first substrate. The semiconductor image sensor further includes an interconnect structure electrically connected to the pixel. The semiconductor image sensor further includes a reflection structure between the interconnect and the photodiode, wherein the reflection structure is configured to reflect light passing through the photodiode back toward the photodiode.

Abstract: A transistor substrate is provided. The transistor substrate includes a first electrode and a second electrode. The first electrode has a slit. The slit includes a curved portion. The first electrode is used for receiving a common voltage signal. The second electrode overlaps the first electrode. The second electrode and the curved portion of the slit have an overlapping region, and an area of the overlapping region is 0.2 times to 0.8 times an area of the curved portion.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines. The scan lines intersect with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode, a second electrode and a switching transistor. The first electrode has a slit including a major axis portion and a curved portion connected to the major axis portion. One of the first electrode and the second electrode is used for receiving a pixel voltage signal, and the other is used for receiving a common voltage signal. The switching transistor includes a switching electrode. The switching electrode and the curved portion of the slit have an overlapping region, and an area of the overlapping region is 0.2 times to 0.8 times an area of the curved portion.

Abstract: A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines. The scan lines intersect with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode, a second electrode and a switching transistor. The first electrode has a slit including a major axis portion and a curved portion connected to the major axis portion. One of the first electrode and the second electrode is used for receiving a pixel voltage signal, and the other is used for receiving a common voltage signal. The switching transistor includes a switching electrode. The switching electrode and the curved portion of the slit have an overlapping region, and an area of the overlapping region is 0.2 times to 0.8 times an area of the curved portion.

Abstract: A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines, wherein the scan lines intersects with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode having a slit substantially parallel to the data lines. The pixel units include a second electrode and a switching transistor. The switching transistor includes a gate electrode connecting to one of the scan lines. The gate electrode has a first edge substantially parallel to the extending direction of the scan lines. The switching transistor includes a drain electrode electrically connected to one of the first electrode and the second electrode. The drain electrode includes an extending portion which extends toward the slit and extends away from an extending line of the first edge. The drain electrode and the slit have an overlapping region.

Abstract: An electronic device includes: a substrate including a first region and a second region, wherein the first region is in a middle position, and the second region is closer to an edge of the substrate than the first region; a first active layer disposed on the substrate and in the second region; a conducting electrode disposed on the substrate and in the second region, wherein the conducting electrode electrically connects to the first active layer and extends along a first direction; and a conductive layer disposed on the substrate and in the second region, wherein the conductive layer includes an opening, wherein a minimum distance from an edge of the opening to the first active layer along the first direction is different from a minimum distance from another edge of the opening to the first active layer along a second direction different from the first direction.

Abstract: A display panel is disclosed, which includes: a substrate including a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer and a first conducting electrode on the substrate, wherein the first conducting electrode electrically connects to the active layer, and the first conducting electrode extends along a first direction; and a conductive layer disposed on the border region and including an opening, wherein the conductive layer partially overlaps the first conducting electrode in a top view of the border region, wherein a minimum distance from an edge of the opening to the active layer along the first direction is different from a minimum distance from another edge of the opening to the active layer along a second direction, and the first direction is different from the second direction.

Abstract: A glove donning device includes a guide rack having a positioning portion, and a glove providing a connection portion at one side of the glove-wearing mouth thereof and a tear line at the junction of the glove and the connection portion. The connection portion is detachably fastened to the positioning portion of the guide rack to hand down the glove against one side of the guide rack. When the hand is wearing the glove, the guide rack holds the glove in place so that the glove will not move arbitrarily, and the user's hand can be easily and smoothly worn by the glove-wearing mouth into the glove by a one-handed movement. Then, the hand is pulled outward to tear the tear line apart, so that the glove can be easily disconnected from the connection portion. This design solves the disadvantage that conventional gloves (such as thin-film gloves) must be worn with both hands.

Abstract: A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines, wherein the scan lines intersects with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode having a slit substantially parallel to the data lines. The pixel units include a second electrode and a switching transistor. The switching transistor includes a gate electrode connecting to one of the scan lines. The gate electrode has a first edge substantially parallel to the extending direction of the scan lines. The switching transistor includes a drain electrode electrically connected to one of the first electrode and the second electrode. The drain electrode includes an extending portion which extends toward the slit and extends away from an extending line of the first edge. The drain electrode and the slit have an overlapping region.

Abstract: A retargeting method for optical proximity correction (OPC) is provided. The method includes: assigning evaluation points for defining profile of a layout pattern; identifying critical regions of the layout pattern that could result in limitation on the process window of the OPC; categorizing the critical regions based on geometries of the critical regions; obtaining movable ranges and address information of the evaluation points; and shifting the evaluation points according to the parameters obtained during the previous steps.