Patents by Inventor Chun-Lin Lu
Chun-Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11239096Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.Type: GrantFiled: August 11, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
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Publication number: 20220028773Abstract: A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Lu, Jiun-Yi Wu, Kai-Chiang Wu
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Patent number: 11211358Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.Type: GrantFiled: December 16, 2019Date of Patent: December 28, 2021Assignee: Taiwwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
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Patent number: 11211339Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.Type: GrantFiled: December 4, 2019Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
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Publication number: 20210391230Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
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Patent number: 11183461Abstract: A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.Type: GrantFiled: January 7, 2020Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chun-Lin Lu
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Patent number: 11145595Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.Type: GrantFiled: December 8, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
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Patent number: 11114357Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.Type: GrantFiled: September 30, 2019Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
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Patent number: 11101238Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.Type: GrantFiled: March 20, 2018Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Kai Liu, Chun-Lin Lu, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chia-Chun Miao
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Publication number: 20210210450Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: CHUN-LIN LU, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG, SHIH-WEI LIANG, CHING-FENG YANG, CHIA-CHUN MIAO, HAO-YI TSAI
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Publication number: 20210184335Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.Type: ApplicationFiled: August 20, 2020Publication date: June 17, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
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Patent number: 11004810Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.Type: GrantFiled: December 15, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
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Patent number: 10971463Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.Type: GrantFiled: October 30, 2017Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai
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Publication number: 20210091031Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: CHUN-LIN LU, KAI-CHIANG WU
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Publication number: 20210020560Abstract: A package structure includes a first RDL structure, a die, an encapsulant, a film, a TIV and a second RDL structure. The die is located over the first RDL structure. The encapsulant laterally encapsulates sidewalls of the die. The film is disposed between the die and the first RDL structure, and between the encapsulant and the first RDL structure. The TIV penetrates through the encapsulant and the film to connect to the first RDL structure. The second RDL structure is disposed on the die, the TIV and the encapsulant and electrically connected to die and the TIV.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
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Publication number: 20210013151Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
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Patent number: 10868353Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.Type: GrantFiled: April 18, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
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Patent number: 10867952Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad.Type: GrantFiled: May 26, 2020Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Lin Lu, Kai-Chiang Wu
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Patent number: 10867957Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.Type: GrantFiled: December 18, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
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Publication number: 20200373173Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu