Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.

Abstract: A backsheet of a solar cell module including a substrate, a first protection layer, and a second protection layer is provided. The substrate includes a first surface and a second surface opposite to each other. The first protection layer is disposed on the first surface of the substrate. The second protection layer is disposed on the second surface of the substrate, wherein the first protection layer and the second protection layer include a silicone layer. At least one of the first protection layer and the second protection layer includes diffusion particles, wherein the diffusion particles include zinc oxide, titanium dioxide modified with silicon dioxide, or a combination thereof. A thickness of the first protection layer and a thickness of the second protection layer are respectively 10 ?m to 30 ?m. A solar cell module including the backsheet is also provided.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i?2.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.

Abstract: A method of fabricating a semiconductor device, including the following steps. A plurality of fin structures are formed on a substrate. There is a trench between the fin structures. At least two times of circulating processes are performed. The circulating processes include: a deposition process and an etching process. The deposition process is performed to fill a first conductor material layer in the trench. The first conductor material layer covers top parts and sidewalls of the fin structures. The etching process is performed to remove a part of the first conductor material layer.

Abstract: A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.

Abstract: A blocking semiconductor layer minimizes penetration of implant species into a semiconductor layer beneath the blocking semiconductor layer. The blocking semiconductor layer may have grains with relatively fine or small grain sizes and/or may have a dopant in a relatively low concentration to minimize penetration of implant species into the semiconductor layer beneath the blocking semiconductor layer.

Abstract: A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.

Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.

Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.

Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.

Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.

Abstract: A method for in-gas micro/nanoimprinting of bulk metallic glass includes steps of preparing a die, heating the bulk metallic glass and in-gas micro/nanoimprinting of the bulk metallic glass. In the step of preparing a die, the die has a micro/nano structure having multiple depressions and a flow channel connected to the depressions. In the step of heating the bulk metallic glass, the bulk metallic glass is heated to a temperature between a glass transition temperature and a crystallization temperature of the bulk metallic glass. In the step of in-gas micro/nanoimprinting, the bulk metallic glass is forced into the die in presence of gas to imprint a complementing micro/nano structure on the bulk metallic glass. Because the die has a flow channel to allow air or gas to escape from the micro/nano structure of the die, the micro/nanoimprinting can be performed in presence of air or gas.