Patents by Inventor Chun-Ling Lin
Chun-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240162359Abstract: A backsheet of a solar cell module including a substrate, a first protection layer, and a second protection layer is provided. The substrate includes a first surface and a second surface opposite to each other. The first protection layer is disposed on the first surface of the substrate. The second protection layer is disposed on the second surface of the substrate, wherein the first protection layer and the second protection layer include a silicone layer. At least one of the first protection layer and the second protection layer includes diffusion particles, wherein the diffusion particles include zinc oxide, titanium dioxide modified with silicon dioxide, or a combination thereof. A thickness of the first protection layer and a thickness of the second protection layer are respectively 10 ?m to 30 ?m. A solar cell module including the backsheet is also provided.Type: ApplicationFiled: January 9, 2023Publication date: May 16, 2024Applicant: Industrial Technology Research InstituteInventors: Chih-Kang Peng, Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang
-
Publication number: 20240145641Abstract: A color conversion panel and a display device are provided. The color conversion panel includes an opaque substrate and a sapphire substrate. The opaque substrate includes a plurality of first pixel openings, a plurality of second pixel openings and a plurality of third pixel openings. The first pixel openings are filled with red quantum dot material, and the second pixel openings are filled with green quantum dot material. The sapphire substrate is on the opaque substrate. A first surface of the sapphire substrate that faces the opaque substrate has a plurality of first arc surfaces corresponding to the first pixel openings, a plurality of second arc surfaces corresponding to the second pixel openings, and a plurality of third arc surfaces corresponding to the third pixel openings.Type: ApplicationFiled: December 15, 2022Publication date: May 2, 2024Applicant: Industrial Technology Research InstituteInventors: Kai-Ling Liang, Wei-Hung Kuo, Hui-Tang Shen, Chun-I Wu, Suh-Fang Lin
-
Publication number: 20240124844Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 18, 2024Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
-
Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
-
Publication number: 20230263402Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining smoothness of the waveform segments; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the waveform segments, and generating a detection result.Type: ApplicationFiled: June 23, 2022Publication date: August 24, 2023Applicants: Giant Power Technology Biomedical Corp., National Taipei University of TechnologyInventors: CHIEN-JEN WANG, Po-En Liu, Shu-Hung Chao, Ming-Kun Huang, Ing-Lan Liou, Chun- Young Chang, Chin-Kun Tseng, Zi-Yi Zhuang, Ya-Wen Chao, Hsuan-Yu Liu, Gu-Neng Wu, Chun-Ling Lin, Yuh-Shyan Hwang, San-Fu Wang, I-Chyn Wey, Jason King
-
Publication number: 20230263467Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining systolic peaks for determining first and second portions of the waveform segments; determining smoothness of the second portions; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the second portions, and generating a detection result.Type: ApplicationFiled: June 23, 2022Publication date: August 24, 2023Applicants: Giant Power Technology Biomedical Corp., National Taipei University of TechnologyInventors: Po-En Liu, Shu-Hung Chao, Ming-Kun Huang, Chien-Jen Wang, Ing-Lan Liou, Chun- Young Chang, Chin-Kun Tseng, Zi-Yi Zhuang, Ya-Wen Chao, Hsuan-Yu Liu, Gu-Neng Wu, Chun-Ling Lin, Yuh-Shyan Hwang, San-Fu Wang, I-Chyn Wey, Jason King
-
Publication number: 20230238445Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.Type: ApplicationFiled: February 20, 2022Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
-
Publication number: 20230218268Abstract: A method for detecting a location of a segment of a feeding tube is provided. The feeding tube has a proximal end, a hollow tube body and a distal end, and is placed inside the body of a patient. An audio collecting component is placed on a predetermined part of the patient. The method includes steps of pumping air into the proximal end of the feeding tube, collecting sound to obtain audio data by the audio collecting component, performing audio analysis on the audio data, and determining whether a segment of the hollow tube body is at a part inside the body of the patient that corresponds with the location of the audio collecting component based on result of the audio analysis.Type: ApplicationFiled: June 3, 2022Publication date: July 13, 2023Inventors: Ming-Kun Huang, Chien-Jen Wang, Po-En Liu, Shu-Hung Chao, Ing-Lan Liou, Chun- Young Chang, Chin-Kun Tseng, Zi-Yi Zhuang, Ya-Wen Chao, Hsuan-Yu Liu, Gu-Neng Wu, Chun-Ling Lin, Yuh-Shyan Hwang, San-Fu Wang, I-Chyn Wey, Jason King
-
Publication number: 20200168450Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Applicant: United Microelectronics Corp.Inventors: Ko-Wei Lin, Kuan-Hsiang Chen, Hsin-Fu Huang, Chun-Ling Lin, Sheng-Yi Su, Pei-Hsun Kao
-
Patent number: 10446489Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: October 25, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
-
Patent number: 10323332Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.Type: GrantFiled: July 11, 2016Date of Patent: June 18, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
-
Publication number: 20190067184Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
-
Patent number: 10153231Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: March 22, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
-
Patent number: 10079177Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.Type: GrantFiled: September 1, 2017Date of Patent: September 18, 2018Assignee: United Microelectronics Corp.Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
-
Publication number: 20180261537Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: March 22, 2017Publication date: September 13, 2018Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
-
Publication number: 20180138263Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.Type: ApplicationFiled: November 14, 2016Publication date: May 17, 2018Inventors: Ko-Wei Lin, Yen-Chen Chen, Chin-Fu Lin, Chun-Yuan Wu, Chun-Ling Lin
-
Patent number: 9966425Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.Type: GrantFiled: February 28, 2017Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
-
Patent number: 9685316Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.Type: GrantFiled: February 25, 2013Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
-
Publication number: 20160319450Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.Type: ApplicationFiled: July 11, 2016Publication date: November 3, 2016Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
-
Publication number: 20160276215Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.Type: ApplicationFiled: March 18, 2015Publication date: September 22, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: PEI-TING LEE, GUO-WEI CHEN, CHUN-LING LIN, CHI-MAO HSU, CHING-WEI HSU, HUEI-RU TSAI, JIA-RONG LI, SHANG NAN CHOU, PO CHIH WU