Patents by Inventor Chun-Ming Hu
Chun-Ming Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134287Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Publication number: 20230065557Abstract: A two-phase cold plate includes a base, an upper cover, a heat exchange cavity and a cooling fin module. The upper cover is installed on the base, the heat exchange cavity is formed between the base and the upper cover, and the cooling fin module is installed in the heat exchange cavity. The upper cover includes at least one nozzle module and a plurality of two-phase fluid channels. The two-phase fluid channels are respectively located on both sides of the nozzle module, and the nozzle module sprays a heat dissipating fluid to the cooling fin module, and the heat dissipating fluid flows along the cooling fin module to the two-phase fluid channels on both sides of the cooling fin module to cool the cooling fin module.Type: ApplicationFiled: July 11, 2022Publication date: March 2, 2023Inventors: Chien-Yu CHEN, Tian-Li YE, Chun-Ming HU
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Patent number: 11513444Abstract: The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.Type: GrantFiled: June 15, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Publication number: 20220248570Abstract: A coolant distribution unit includes a casing, a control module, a power supply module, a heat exchange module, an integrated pipe, and a fluid driving module. The power supply module is electrically connected to the control module, the integrated pipe includes a plurality of inlets and an outlet to collect and output a cooled working fluid, the fluid driving module is electrically connected to the control module and the power supply module, and the fluid driving module is in fluid communication with the heat exchange module. The control module, power supply module, heat exchange module, integrated pipe, and fluid driving module are all arranged in the casing.Type: ApplicationFiled: January 19, 2022Publication date: August 4, 2022Inventors: Chien-Yu CHEN, Tian-Li YE, Chun-Ming HU
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Publication number: 20220100103Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.Type: ApplicationFiled: March 10, 2021Publication date: March 31, 2022Inventors: Hung-Chung CHIEN, Hao-Ken HUNG, Chih-Chieh YANG, Ming-Feng SHIEH, Chun-Ming HU
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Patent number: 11287746Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.Type: GrantFiled: March 10, 2021Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chung Chien, Hao-Ken Hung, Chih-Chieh Yang, Ming-Feng Shieh, Chun-Ming Hu
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Patent number: 10867116Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: December 18, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20200310255Abstract: The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Patent number: 10684556Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.Type: GrantFiled: May 3, 2019Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Publication number: 20200125785Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Patent number: 10521548Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: July 23, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20190258179Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Patent number: 10281827Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.Type: GrantFiled: July 7, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Publication number: 20180330040Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: July 23, 2018Publication date: November 15, 2018Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Patent number: 10031997Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: GrantFiled: December 21, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20180196911Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.Type: ApplicationFiled: December 21, 2016Publication date: July 12, 2018Inventors: Yang-Hung Chang, Che-Yuan Sun, Chih-Ming Ke, Chun-Ming Hu
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Publication number: 20180173110Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.Type: ApplicationFiled: July 7, 2017Publication date: June 21, 2018Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
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Patent number: 9455156Abstract: A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set.Type: GrantFiled: September 24, 2015Date of Patent: September 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bi-Ming Yen, Tsai-Chun Li, Chun-Ming Hu
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Publication number: 20160013071Abstract: A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set.Type: ApplicationFiled: September 24, 2015Publication date: January 14, 2016Inventors: Bi-Ming YEN, Tsai-Chun LI, Chun-Ming HU
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Patent number: 9159580Abstract: A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.Type: GrantFiled: December 14, 2012Date of Patent: October 13, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bi-Ming Yen, Tsai-Chun Li, Chun-Ming Hu