Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

Abstract: A control circuit of a power converter includes a sensing circuit, a ramp signal generation circuit and a PWM circuit. The sensing circuit, coupled to an output circuit, provides a current sensing signal. The ramp signal generation circuit includes a transient circuit and a signal generation circuit. The transient circuit receives the current sensing signal and generates a variable reference voltage. The signal generation circuit provides a ramp signal according to the variable reference voltage. The PWM circuit provides a PWM signal to the output circuit according to the ramp signal. When current sourcing occurs, it continues for a first default time. A transient state during current sourcing continues for a second default time less than first default time. The variable reference voltage is changed from a default value to an adjusted value during the second default time and restored to the default value after the second default time.

Abstract: A method for debugging a program, based on simulating an object program and comparing simulated waveforms with standard waveforms are applied in an electronic device. A simulated environment corresponding to the object program is established and multiple instructions from code of the object program are mapped against the standard waveforms. Trigger points are set in the object program, the object program is run from the trigger point and simulation waveforms are stored. The simulation waveforms are compared with the standard waveforms, and the location of a bug of the object program is found according a comparison. The bug may be resolved or cured. The electronic device utilizing the method is also disclosed.

Abstract: A control circuit of a power converter includes a sensing circuit, a ramp signal generation circuit and a PWM circuit. The sensing circuit, coupled to an output circuit, provides a current sensing signal. The ramp signal generation circuit includes a transient circuit and a signal generation circuit. The transient circuit receives the current sensing signal and generates a variable reference voltage. The signal generation circuit provides a ramp signal according to the variable reference voltage. The PWM circuit provides a PWM signal to the output circuit according to the ramp signal. When current sourcing occurs, it continues for a first default time. A transient state during current sourcing continues for a second default time less than first default time. The variable reference voltage is changed from a default value to an adjusted value during the second default time and restored to the default value after the second default time.

Abstract: A method for debugging a program, based on simulating an object program and comparing simulated waveforms with standard waveforms are applied in an electronic device. A simulated environment corresponding to the object program is established and multiple instructions from code of the object program are mapped against the standard waveforms. Trigger points are set in the object program, the object program is run from the trigger point and simulation waveforms are stored. The simulation waveforms are compared with the standard waveforms, and the location of a bug of the object program is found according a comparison. The bug may be resolved or cured. The electronic device utilizing the method is also disclosed.

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: A method for accessing a data bus includes setting a first-come-first-served basis for determining priorities between masters in addition to a fixed priority being set between the same masters. A number of master ports are connected to a number of masters, and a number of slave ports are connected to a number of slaves. First and second multiplexers are connected between the master ports and the slave ports, a number of decoders are connected to the second multiplexers, and a number of arbiters are connected to the first multiplexers. The master ports have a fixed priority, but each arbiter, in receiving an access-request signal sent by a master port, can determine an order as to which of multiple master ports can access a slave port according to a combination of the fixed priority basis and the first-come-first-served basis. A system and a relevant device are also disclosed.

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: A flexible web for clothing comprises a fabric substrate and a lining piece unit. The fabric substrate layer has a plurality of slits which are displaced from each other and each of which includes a first slit segment and a second slit segment. The lining piece unit is made from an absorbent polymer and includes a plurality of lining pieces each of which has a first marginal edge and a second marginal edge, and each of which is configured such that when bonded to the fabric substrate layer, the first and second marginal edges respectively border at the first and second slit segments.

Abstract: An apparatus and method for forwarding a web address to another web address is presented. A web forwarder receives a request destined to a first web address including at least a domain name. The web forwarder then determines a forwarding uniform resource locator (URL) that corresponds to the domain name and redirects the request to a second web address that corresponds to the forwarding URL.

Abstract: A fan module includes a casing, a fan, and two vibration absorption assemblies. The casing has an accommodating space. The fan is located in the accommodating space and keeps a distance from the casing. Each of the two vibration absorption assemblies includes two first vibration absorption components and a second vibration absorption component. The two first vibration absorption components are respectively in contact with the fan and separated from the casing, respectively. The second vibration absorption component is connected with two first vibration absorption components and the casing, respectively. The first vibration absorption components and the second vibration absorption components are adapted for absorbing the vibration waves having different frequency ranges.

Abstract: A fan module includes a casing, a fan, and two vibration absorption assemblies. The casing has an accommodating space. The fan is located in the accommodating space and keeps a distance from the casing. Each of the two vibration absorption assemblies includes two first vibration absorption components and a second vibration absorption component. The two first vibration absorption components are respectively in contact with the fan and separated from the casing, respectively. The second vibration absorption component is connected with two first vibration absorption components and the casing, respectively. The first vibration absorption components and the second vibration absorption components are adapted for absorbing the vibration waves having different frequency ranges.

Abstract: A fan structure includes a casing, a fan, and two elastic members. The casing has an accommodation space. The fan is located in the accommodation space. The fan has a first side and a second side opposite to each other. One of the two elastic members is sandwiched between the casing and the first side of the fan. The other one of the two elastic members is sandwiched between the casing and the second side of the fan. The two elastic members normally keep the fan away from the casing, so as to make the fan contact the casing through the two elastic members, thereby achieving a damping effect.

Abstract: An apparatus and method for forwarding a web address to another web address is presented. A web forwarder receives a request destined to a first web address including at least a domain name. The web forwarder then determines a forwarding uniform resource locator (URL) that corresponds to the domain name and redirects the request to a second web address that corresponds to the forwarding URL.

Abstract: An apparatus and method for forwarding a web address to another web address is presented. A web forwarder receives a request destined to a first web address including at least a domain name. The web forwarder then determines a forwarding uniform resource locator (URL) that corresponds to the domain name and redirects the request to a second web address that corresponds to the forwarding URL.

Abstract: A flash memory circuit has both SATA and USB interfaces. When the flash memory circuit is coupled to a computer, the flash memory circuit utilizes the transmitted power from the computer through the USB interface for operating, and communicates with the computer through the faster SATA interface for data accessing of the flash memory.

Abstract: An apparatus and method for forwarding a web address to another web address is presented. A web forwarder receives a request destined to a first web address including at least a domain name. The web forwarder then determines a forwarding uniform resource locator (URL) that corresponds to the domain name and redirects the request to a second web address that corresponds to the forwarding URL.