Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.

Abstract: In a method for detecting equivalent series inductances (ESL) of an electrical component of a printed circuit board (PCB), the electrical component and one or more signal lines connected with the electrical component are selected from a layout diagram of the PCB. The method selects a standard range of the ESL of the selected electrical component, calculates an ESL between each of the signal lines and a via hole corresponding to the signal line, and determines signal lines having ESL value that are not within the standard range. The method locates attribute data of the determined signal lines and the selected electrical component in the layout diagram of the PCB, and displays the attribute data of the determined signal lines and the selected electrical component on a display device.

Abstract: In a method for detecting equivalent series inductances (ESL) of an electrical component of a printed circuit board (PCB), the electrical component and one or more signal lines connected with the electrical component are selected from a layout diagram of the PCB. The method selects a standard range of the ESL of the selected electrical component, calculates an ESL between each of the signal lines and a via hole corresponding to the signal line, and determines signal lines having ESL value that are not within the standard range. The method locates attribute data of the determined signal lines and the selected electrical component in the layout diagram of the PCB, and displays the attribute data of the determined signal lines and the selected electrical component on a display device.

Abstract: A system and method for testing size of vias reads a component group from a storage system and reads a via size of each via in the component group. If the via size of a via accords with a standard size corresponding to the component group, the via is determined as a qualified via. If the via size of a via does not accord with the standard size, the via is determined as an unqualified via. The unqualified via is highlighted on a printed circuit board (PCB) design map displayed on a display.

Abstract: A system and method for testing size of vias reads a component group from a storage system and reads a via size of each via in the component group. If the via size of a via accords with a standard size corresponding to the component group, the via is determined as a qualified via. If the via size of a via does not accord with the standard size, the via is determined as an unqualified via. The unqualified via is highlighted on a printed circuit board (PCB) design map displayed on a display.

Abstract: A method for checking a length of a wire path between a capacitor and a via of the PCB design obtains length criteria and information on capacitors from a database, selects one or more capacitors and pins of the selected capacitors from the obtained information on capacitors and selects one of the length criteria, and obtains positions of selected capacitors and positions of vias corresponding to the positions of selected capacitors from the database. The method further calculates each length of a wire path between a selected capacitor and a corresponding via according to the position of the capacitor and the position of the via, determines whether each calculated length of a wire path between a selected capacitor and a corresponding via is acceptable according to a comparison with the selected length criterion, and outputs check results of the determining step.

Abstract: A method for selecting a ferrite bead for a filter to avoid a peak value in a frequency response curve of the filter is provided. The method includes the steps of: building an equivalent model database including parameters of equivalent models of ferrite beads, the parameters including an inductance and a capacitance of a corresponding equivalent model of each ferrite bead; calculating parameters of a desired ferrite bead in the filter based on parameters of the filter, the parameters of the ferrite bead including an inductance, a capacitance, and a resonant frequency; adjusting parameters of the filter until the calculated resonant frequency equals or approaches a desired resonant frequency, and finding an inductance and a capacitance respectively equaling or approaching the calculated inductance and the calculated capacitance in the database; and selecting a ferrite bead with the appropriate inductance and capacitance as found in the database for the filter.

Abstract: A system for checking a reference plane of a signal trace in a PCB includes: a database, a signal filter, a signal trace selecting unit, a reference plane checking unit and a display unit. The database is configured for storing a plurality of signal files. The signal file in the PCB constitutes one or more signal groups. Each signal group has a same bus. The signal filter is configured for filtering a signal group from a signal file. The signal trace selecting unit is configured for selecting a signal for checking, from the signal group, and for selecting a trace corresponding to the signal. The reference plane checking unit is configured for checking the integrity of a reference plane that is nearest to the selected signal trace through orthographically projecting the selected signal trace to the reference plane and for checking a relationship between the reference plane and the projection. A related method is also disclosed.

Abstract: A method for checking a length of a wire path between a capacitor and a via of the PCB design is disclosed. The method includes: obtaining length criteria and information on capacitors from a database; selecting one or more capacitors and pins of selected capacitors from the obtained information on capacitors, and selecting one of the length criteria; obtaining positions of selected capacitors, and positions of vias corresponding to the positions of selected capacitors from the database; calculating each length of a wire path between a selected capacitor and a corresponding via according to the position of the capacitor and the position of the via; determining whether each calculated length of a wire path between a selected capacitor and a corresponding via is acceptable according to a comparison with the selected length criterion; and outputting check results of the determining step. A related system is also disclosed.

Abstract: A system for checking a reference plane of a signal trace in a PCB includes: a database, a signal filter, a signal trace selecting unit, a reference plane checking unit and a display unit. The database is configured for storing a plurality of signal files. The signal file in the PCB constitutes one or more signal groups. Each signal group has a same bus. The signal filter is configured for filtering a signal group from a signal file. The signal trace selecting unit is configured for selecting a signal for checking, from the signal group, and for selecting a trace corresponding to the signal. The reference plane checking unit is configured for checking the integrity of a reference plane that is nearest to the selected signal trace through orthographically projecting the selected signal trace to the reference plane and for checking a relationship between the reference plane and the projection. A related method is also disclosed.

Abstract: A method for selecting a ferrite bead for a filter to avoid a peak value in a frequency response curve of the filter is provided. The method includes the steps of: building an equivalent model database including parameters of equivalent models of ferrite beads, the parameters including an inductance and a capacitance of a corresponding equivalent model of each ferrite bead; calculating parameters of a desired ferrite bead in the filter based on parameters of the filter, the parameters of the ferrite bead including an inductance, a capacitance, and a resonant frequency; adjusting parameters of the filter until the calculated resonant frequency equals or approaches a desired resonant frequency, and finding an inductance and a capacitance respectively equaling or approaching the calculated inductance and the calculated capacitance in the database; and selecting a ferrite bead with the appropriate inductance and capacitance as found in the database for the filter.