Patents by Inventor Chunshan Yin
Chunshan Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11404532Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.Type: GrantFiled: July 29, 2020Date of Patent: August 2, 2022Assignee: NXP B.V.Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
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Publication number: 20200357881Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
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Patent number: 10770539Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.Type: GrantFiled: September 25, 2018Date of Patent: September 8, 2020Assignee: NXP B.V.Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
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Patent number: 10680087Abstract: An integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has an elevated gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusion has a base region and an annular side region located between the base region and the elevated gate such that the diffusions have increased lateral surface areas that support greater current levels for the diode finger, which enables gated diodes to be implemented with fewer fingers and therefore less layout area than equivalent conventional gated diodes that do not have elevated gates. The first gated diode can be implemented with an analogous second gated diode to form ESD-protection circuitry for the integrated circuit.Type: GrantFiled: September 5, 2018Date of Patent: June 9, 2020Assignee: NXP B.V.Inventors: Cheong Min Hong, Chunshan Yin, Yu Chen
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Publication number: 20200098850Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
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Publication number: 20200075751Abstract: An integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has an elevated gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusion has a base region and an annular side region located between the base region and the elevated gate such that the diffusions have increased lateral surface areas that support greater current levels for the diode finger, which enables gated diodes to be implemented with fewer fingers and therefore less layout area than equivalent conventional gated diodes that do not have elevated gates. The first gated diode can be implemented with an analogous second gated diode to form ESD-protection circuitry for the integrated circuit.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Cheong Min Hong, Chunshan Yin, Yu Chen
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Patent number: 9281308Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.Type: GrantFiled: July 22, 2014Date of Patent: March 8, 2016Assignee: Globalfoundries Singapore Pte., Ltd.Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan
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Patent number: 9087813Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.Type: GrantFiled: February 6, 2014Date of Patent: July 21, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shyue Seng Tan, Lee Wee Teo, Chunshan Yin
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Publication number: 20140332902Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.Type: ApplicationFiled: July 22, 2014Publication date: November 13, 2014Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan
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Patent number: 8824208Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.Type: GrantFiled: May 10, 2013Date of Patent: September 2, 2014Assignee: Globalfoundries Singapore PTE. Ltd.Inventors: Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan
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Patent number: 8785287Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.Type: GrantFiled: July 6, 2010Date of Patent: July 22, 2014Assignee: Globalfoundries Singapore Pte, Ltd.Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan
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Publication number: 20140151775Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: GLOBAL FOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng TAN, Lee Wee TEO, Chunshan YIN
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Patent number: 8735984Abstract: FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.Type: GrantFiled: July 6, 2010Date of Patent: May 27, 2014Assignee: Globalfoundries Singapore PTE, Ltd.Inventors: Chunshan Yin, Kian Ming Tan, Jae Gon Lee
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Patent number: 8691638Abstract: A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.Type: GrantFiled: December 10, 2010Date of Patent: April 8, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng Tan, Chunshan Yin
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Patent number: 8674457Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.Type: GrantFiled: August 11, 2010Date of Patent: March 18, 2014Assignee: Globalfoundries Singapore PTE., Ltd.Inventors: Eng Huat Toh, Elgin Quek, Chunshan Yin, Chung Foong Tan, Jae Gon Lee
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Patent number: 8647946Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.Type: GrantFiled: November 19, 2009Date of Patent: February 11, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shyue Seng Tan, Lee Wee Teo, Chunshan Yin
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Patent number: 8633081Abstract: A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.Type: GrantFiled: December 29, 2010Date of Patent: January 21, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Chunshan Yin, Palanivel Balasubramaniam, Jae Gon Lee, Elgin Quek
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Publication number: 20130328118Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.Type: ApplicationFiled: May 10, 2013Publication date: December 12, 2013Applicant: Globalfoundries Singapore PTE. LTD.Inventors: Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan
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Patent number: 8563386Abstract: A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.Type: GrantFiled: November 16, 2010Date of Patent: October 22, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Chung Foong Tan, Eng Huat Toh, Jae Gon Lee, Chunshan Yin, Lakshmi Bera
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Patent number: 8530310Abstract: A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.Type: GrantFiled: December 31, 2009Date of Patent: September 10, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Chunshan Yin, Shyue Seng Tan, Chung Foong Tan, Jae Gon Lee, Elgin Quek, Purakh Raj Verma